MP8759 – 26V, 8A, SYNCHRONOUS, STEP-DOWN CONVERTER

MP8759 Rev. 1.1

www.MonolithicPower.com

15

4/13/2017

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© 2017 MPS. All Rights Reserved.

APPLICATION INFORMATION

COMPONENT SELECTION

Setting the Output Voltage with an E-

Capacitor or POS Capacitor

For applications that use an electrolytic capacitor

or POS capacitor with a controlled ESR output is

set

as

an

output

capacitor,

external

compensation is not need. The output voltage is

set by feedback resistors R1 and R2 (see Figure

6).

Figure 6: Simplified Circuit of POS Capacitor

The value for R2 must be chosen carefully since

a small R2 value leads to considerable quiescent

current loss, while a value that is too large makes

FB noise sensitive. R2 is recommended to be

within 5kΩ - 100kΩ. Typically, set the current

through R2 between 5µA - 30µA to create a good

balance between the system stability and no-load

loss. Considering the output ripple, calculate R1

with Equation (3):

OUT

REF

REF

VV

R1

R2

V





(3)

Setting the Output Voltage with a Pure

Ceramic Output Capacitor

The

MP8759

employs

internal

ramp

compensation. When the internal compensation

is enough for a stable operation with the ceramic

output capacitors, the external resistor divider is

used to set VOUT. First, choose a value for R2.

Then R1 can be determined with Equation (4):

OUT

REF

REF

VV

R1

R2

V





(4)

The feedback circuit is shown in Figure 7.

Figure 7: Feedback Network

When the internal ramp compensation is not

enough to stabilize the loop with a pure ceramic

capacitor, an extra external voltage ramp around

20mV should be added to FB through resistor R4

and capacitor C5.

Figure 8: External Ramp Compensation

Figure 8 shows a simplified external ramp

be estimated with Equation (5):







in

out

ramp

on

45

VV

VT

RC

(5)

For better load or line regulation, use a lower

around 20mV.

The MP8759 employs a DC auto-tune loop to

can maintain 0.6V, even with an external ramp

compensation circuit. Figure 9 shows the DC

equivalent circuit with an external ramp circuit.

R1

R2

R4

R9

Figure 9: Equivalent DC Circuit

R1

R2

ESR

POSCAP

SW

FB

Vo

L