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W209C
PRELIMINARY
Document #: 38-07171 Rev. *A
Page 13 of 16
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Group Skew and Jitter Limits
Output Group
Pin-Pin Skew Max.
Cycle-Cycle Jitter
Duty Cycle
Nom Vdd
Skew, Jitter
Measure
Point
Typical Output
Impedance
CPU
175 ps
250 ps
45/55
2.5V
1.25V
21
Ω
SDRAM
250 ps
250 ps
45/55
3.3V
1.5V
14
Ω
APIC
250 ps
500 ps
45/55
2.5V
1.25V
16
Ω
48MHz
250 ps
500 ps
45/55
3.3V
1.5V
21
Ω
3V66
175 ps
500 ps
45/55
3.3V
1.5V
14
Ω
PCI
500 ps
500 ps
45/55
3.3V
1.5V
14
Ω
REF
N/A
1000 ps
45/55
3.3V
1.5V
11
Ω
Clock Output Wave
2.5V Clocking
3.3V Clocking
Test Point
Test Load
TPERIOD
Duty Cycle
THIGH
2.0
1.25
0.4
TLOW
TRISE
TFALL
TLOW
TRISE
TFALL
TPERIOD
Duty Cycle
THIGH
2.4
1.5
0.4
Output
Buffer
Interface
Interface
Figure 8. Output Buffer
Ordering Information
Ordering Code
Package Name
Package Type
W209C
H
48-pin SSOP (300 mils)
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