CM6535 datasheet(4/57 Pages) CMEDIA

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CM6535

USB Audio Chip

Page 4 / 57

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6.6.4

2S Mode ..........................................................................................................................27

6.6.5

2S MCLK/BCLK/LRCK ratio and format for cm6535 ..................................................28

6.6.6

I2S output enable setting and data stream path................................................................29

6.6.7

2S DSP mode...................................................................................................................30

6.7

SPDIF control description........................................................................................................31

6.7.1

SPDIF frame description..................................................................................................31

6.7.2

SPDIF out channel status .................................................................................................32

6.8

Digital microphone ..................................................................................................................33

6.9

2C interface .............................................................................................................................34

6.9.1

2C master mode...............................................................................................................34

6.9.2

I2C-master read with clk_sync mode ..............................................................................35

6.9.3

2C master device address and control register ................................................................35

6.9.4

2C master memory address pointer (map) register .........................................................35

6.9.5

2C master memory address pointer (map2) register .......................................................35

6.9.6

2C master data register....................................................................................................35

6.9.7

2C Master Control and Status Register 0 ........................................................................36

6.9.8

2C master control and status register 1 ...........................................................................36

6.9.9

2C master download control and status register..............................................................36

6.9.10

2C master clock period setting register ...........................................................................37

6.9.11

2C slave mode .................................................................................................................38

6.9.12

2C slave data register ......................................................................................................38

6.9.13

2C slave status register....................................................................................................38

6.9.14

2C slave memory address pointer (map) register............................................................39

6.9.15

2C slave status register....................................................................................................39

6.10

SPI interface.............................................................................................................................41

6.10.1

SPI Registers Descriptions...............................................................................................41

6.10.2

SPI Control Register 0 .....................................................................................................41

6.10.3

SPI control register 1 .......................................................................................................42

6.10.4

SPI interrupt .....................................................................................................................42

6.10.5

SPI Control Register 3 .....................................................................................................43

6.11

GPIO ........................................................................................................................................44

6.11.1

GPO data register .............................................................................................................44

6.11.2

GPI data register ..............................................................................................................44

6.11.3

GPIO direction control register........................................................................................44

6.11.4

GPIO interrupt enable mask register................................................................................44

6.11.5

GPIO debouncing register................................................................................................44

6.11.6

GPI remote choose ...........................................................................................................44

6.11.7

GPIO pull-up/down..........................................................................................................45

6.12

Arbitrary sine-tone generator ...................................................................................................47

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