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dc1996afb

DEMO MANUAL DC1996A

SIGNAL CONNECTIONS

J1 CLK IN: This input has a 50Ω termination resistor,

and is intended to be driven by a low jitter 10dBm sine or

square wave. To achieve the full AC performance of this

part, the clock jitter should be kept under 2ps. This input

is capacitively coupled so that the input clock can be either

0V to 3.3V or ±1.65V. This eliminates the need for level

shifting. To run at the maximum conversion rate, apply

the frequency specified in the Table 1.

J2 Ch2+ Input: In the single-ended configuration, this is

the channel 2 signal input. For differential operation, this

serves as the positive channel 2 signal input.

J3 Ch2– Input: This input is used only for differential

operation. It serves as the negative channel 2 signal input.

J4 Ch1+ Input: In the single-ended configuration, this is

the channel 1 signal input. For differential operation, this

serves as the positive channel 1 signal input.

J5 Ch1– Input: This input is used only for differential

operation. It serves as the negative channel 1 signal input.

J6 FPGA Program: Factory use only.

J7 JTAG: Factory use only.

JP1 +IN2 Coupling: Use this jumper to select AC- or DC-

coupling of the signal applied to J2. The default setting

is DC. At very low input frequencies, using AC-coupling

may degrade the distortion performance.

JP2 Mode: Use this jumper to select the signal input mode

for the channel 2 input of the LTC2323. The default setting

is Diff. The Diff setting accepts a single-ended signal from

J2 and applies it as a differential signal to channel 2 of the

LTC2323. The Bip setting accepts a single-ended signal

from J2 and applies it as a single-ended bipolar signal to

channel 2 of the LTC2323. The Uni setting also accepts a

single-ended signal from J2, but applies it as a unipolar

signal to channel 2 of the LTC2323.

JP3 Data Out: Use this jumper to select the data output

format from the LTC2323. The default setting is CMOS.

The output data will not be valid if the jumper is moved

to the LVDS position unless the following changes have

been made:

Install 100Ω S0402 resistors at R26, 75, 76, 99

Reprogram the CPLD through J6 using the program-

ming file LTC2323.pof found at:

http://www.linear.com/demo/DC1996A

Move JP3 to the LVDS position.

JP4 –IN2 Coupling: Use this jumper to select AC- or DC-

coupling of the signal applied to J3. The default setting

is DC. At very low input frequencies, using AC-coupling

may degrade the distortion performance.

JP5 +IN1 Coupling: Use this jumper to select AC- or DC-

coupling of the signal applied to J4. The default setting

is DC. At very low input frequencies, using AC-coupling

may degrade the distortion performance.

JP6 CM1: Use this jumper to set the DC bias point for the

signal applied to J4 when JP5 (+IN1 coupling) is in the

AC position. The default setting is ADC. The EXT setting

allows the use of an externally applied common mode

voltage applied at E1 (EXT_CM1).

JP7 CM2: Use this jumper to set the DC bias point for the

signal applied to J2 when JP1 (+IN2 coupling) is in the

AC position. The default setting is ADC. The EXT setting

allows the use of an externally applied common mode

voltage applied at E2 (EXT_CM2).

JP8 Mode: Use this jumper to select the signal input mode

for the channel 1 input of the LTC2323. The default setting

is Diff. The Diff setting accepts a single-ended signal from

J4 and applies it as a differential signal to channel 1 of the

LTC2323. The Bip setting accepts a single-ended signal

from J4 and applies it as a single-ended bipolar signal to

channel 1 of the LTC2323. The Uni setting also accepts a

single-ended signal from J4, but applies it as a unipolar

signal to channel 1 of the LTC2323.

HARDWARE SETUP