MP3332

MP3332 Rev. 1.0

www.MonolithicPower.com

16

5/1/2018

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2018 MPS. All Rights Reserved.

Current Reduction

When the MP3332 works in flash mode, the

output current may drop due to the following

conditions:

1. TX is High

TX is used to synchronize the RF transmission

signal (see Figure 14). If TX goes high during

flash mode, the flash current drops to the

current set by I_TX in less than 5µs and sets

the FT_TX bit to 1. If TX goes low, the current

ramps up to the flash current again.

MP3332 Software and Edge Sensitive

Flash Mode w/ TX is Active:

ILED1

ILED2

I2C

REG 0x01,

STR_MOD=0

LED_MOD=11

REG 0x06/7,

I1_FL=XXXX

I2_FL=XXXX

REG 0x08/9,

I1_TX=XXXX

I2_TX=XXXX

REG 0x03,

FL_TIM=XXXX

REG 0x01,

LED1_EN=1

LED2_EN=1

Reset,

LED1_EN to 0

LED2_EN to 0

LED_MOD to 00

FL_TIMER

TX

Figure 14: TX High

2. Input DC Current Limit is Triggered

The MP3332 uses the input DC current limit

protection to avoid drawing excessive current

from the battery. Since the input current limit is

sensed in the NMOS switch, it is effective only

in

boost

mode.

This

current

can

be

programmed by the IL_DC register from 1A to

4.2A. If the input current hits the input current

limit threshold, the LED output current holds

until the input current limit drops below the

current limit threshold. The fault bit FT_IDC is

set to 1 if the input current limit is triggered. The

fault bit remains until it is read back, or the input

power is reset.

3. Low

Battery

Voltage

Threshold

is

Triggered

The

device

provides

low

battery

voltage

protection in flash mode in the following ways:

1. Before the flash, if VBL_SD = 1 and the

input voltage is lower than the threshold

set by VBL_RUN, the device remains

disabled

and

sets

the

fault

bit

FT_VBATL

to

1

(see

Figure

15).

Conversely, if VBL_SD = 0, the device

ramps up to the current set by I_TX and

sets the fault bit FT_VBATL to 1. The

fault bit is cleared after it is read back or

the input power is reset.

2. During the flash pulse, if the battery

voltage drops below the threshold set by

VBL_RUN, the current reduces step-by-

step until the battery voltage reaches

the low battery voltage threshold. The

minimum current caused by current

reduction in the IFL_MIN register can be

read back after the flash. The IFL_MIN

value holds until the next flash occurs,

or the power resets. At this condition,

IFL_MIN can be read and used by

system to set the flash current to ensure

a stable flash current for next flash

operation, which is MP3332 pre-flash

function at low battery voltage.

MP3332 Software and Edge Sensitive

Flash Mode w/ TX is Active:

IFLASH

VBAT

IFLASH Setting value

Voltage drop due

to ESR and Flash

Voltage drop due

to additional load

Report min. IFLASH

Pre-Flash

Adjust IFLASH

VIN_L_RUN

Main-Flash

Figure 15:

Pre-Flash Operation