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LTC4020 Datasheet(PDF) 3 Page - Linear Technology |
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LTC4020 Datasheet(HTML) 3 Page - Linear Technology |
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3 / 42 page ![]() LTC4020 3 4020fd For more information www.linear.com/LTC4020 elecTrical characTerisTics The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C (Note 2). PVIN = SENSVIN = CSP = CSN = BAT = 20V, SHDN = 2V, C(TG1, BG1, TG2, BG2) = 1000pF, VRNG/SS = 2V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS INTVCC Boost Refresh Supply Voltage ILOAD = 5mA l 4.85 5.0 5.15 V Boost Refresh Supply Dropout PVIN = 4.5V; IINTVCC = 5mA 4.46 V Boost Refresh Supply Short-Circuit Current Limit VINTVCC = 0V l 85 150 mA IPVIN PVIN Operating Current Note 3; ITH = 0V l 1.6 3 mA Shutdown Current VSHDN = 0 l 3 6 µA ISENSVIN SENSEVIN Operating Current l 0.25 0.5 mA Shutdown Current VSHDN = 0 l 25 60 µA ISENSTOP SENSETOP Operating Current 32.5 µA Shutdown Current VSHDN = 0 0.1 µA VFBMAX DC/DC Converter Reference Charging Terminated l 2.7 2.75 2.8 V SHDN IC Enable Threshold (Rising) Threshold Hysteresis l 1.175 1.225 100 1.275 V mV SHDN Pin Bias Current 10 nA VSENS DC/DC Converter Inductor Current Limit (Average Value) VSENSVIN – VSENSTOP; VSENSGND – VSENSBOT l 45 50 60 mV Reverse Current Inhibit (Average Value) VITH Falling (TG2 Disabled) VITH Rising (TG2 Enabled) l 0 2 6 mV mV ILIMIT Inductor Current Limit Programming VILIMIT = 0.5V; VILIMIT/VSENS(MAX) 20 V/V ILIMIT Pin Bias Current l 47.5 50 52.5 µA ITH Error Amp Current Limit VFBMAX = 0, VITH = 1.3V 8 µA Error Amp Transconductance VFBMAX = 2.75V; VITH = 1.3V 95 umho VC High Side Current Sense Transconductance (VSENSVIN – VSENSETOP) to IVC VC = 1.8V 200 umho Low Side Current Sense Transconductance (VSENSGND – VSENSEBOT) to IVC VC = 1.8V 200 umho DCMAX Maximum Duty Cycle BG2: tON • fO l 70 80 % fO Switching Frequency RRT = 100k RRT = 50k RRT = 250k l 235 250 500 100 265 kHz kHz kHz tON Minimum On Time BG2 l 150 250 ns tOFF Minimum Off Time TG1 l 300 500 ns tTR Gate Drive Transition Time TG1, BG1, TG2, BG2 5 ns tNOL Gate Drive Non-Overlap time (TG1 – SW1) to BG1, (TG2 – SW2) to BG2 75 ns |
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