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LTC6950 Datasheet(PDF) 7 Page - Linear Technology

Part # LTC6950
Description  1.4GHz Low Phase Noise, Low Jitter PLL with Clock Distribution
PDF  12 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC6950 Datasheet(HTML) 7 Page - Linear Technology

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7
dc1795af
DEMO MANUAL DC1795A
Dc1795a reconfiguration
table 5. loop Filter selection for external oscillator (refer to ClockWizard’s loop Design tab)
DeFAult
oPtion
CloCkWizArD AnD boM Cross reFerenCe
other MoDiFiCAtions
CoMMents
looP Filter tYPe
rz
Ci
CP
instAll
DePoPulAte
Filter 1 (Passive)
RZ_P
CI1_P + CI2_P
CP_P
R68
(0402 0Ω)
R72
Connect CPOUT turret to VTUNE of
external oscillator
Filter 4 (Active)
RZ_A
CI1_A + CI2_A
CP_A
R67, R69
(0402 0Ω)
R70, R72
Select CPINV under the ClockWizard
System tab. Connect CPOUT turret to
VTUNE of external oscillator
typical Dc1795a reQuirements anD characteristics
PArAMeter
inPut or outPut
PhYsiCAl loCAtion
DetAils
3.3V Power Supply
Input
J2 BNC connector, or
V+ = 3.15V to 3.45V turret
Low-noise and spur-free 3.3V,
500mA default (200mA configured*).
Powers LTC6950, U6, U7, U8 and U9
Charge Pump Power Supply
Input
J1 BNC connector, or
V+ to 5.25V turret
Low-noise and spur-free 5V, 35mA*.
Powers LTC6950 and provides common mode to U2
VCXO/VCSO Power Supply
Input
V+ VCXO turret
Low-noise and spur-free 5V, 20mA*. Powers U4
LVDS/CMOS+, LVDS/CMOS–
Two Outputs
J19 and J18 SMA connectors**
DC coupled, 250MHz, (if enabled)*.
Refer to LTC6950 data sheet for output levels for LVDS and
CMOS option.
PECL0+, PECL0–
Two Outputs
J17 and J16 SMA connectors**
AC coupled, 250MHz, 800mVP differential*.
Must have LTC6950’s IBIAS0 = H with default BOM. DC1795A
has options for an external pull down resistor if IBIAS0 = L.
PECL1+, PECL1–
Two Outputs
J13 and J12 SMA connectors**
AC coupled, 250MHz, 800mVP differential (if enabled)*. Must
have LTC6950’s IBIASX = H with default BOM. DC1795A has
options for an external pull down resistor if IBIASX = L.
PECL2+, PECL2–
Two Outputs
J8 and J7 SMA connectors**
PECL3+, PECL3–
Two Outputs
J11 and J10 SMA connectors**
SYNC
Input
SYNC turret or J9 SMA connector EZSync, 0V to 3.3V control signal, refer to the data sheet
STAT1, STAT2
Output
STAT1 and STAT2 turret
STAT1 GREEN LED, if ON LTC6950 is locked*.
STAT2 RED LED, if ON indicates issue*.
Refer to the troubleshooting section and data sheet
Loop Bandwidth
-
Set by loop filter component values 4.2kHz*
VCO Power Supply
Input
V+ VCO turret
Board Modifications required for use, see Table 2
Active Loop Filter Supply
Input
V+ OA turret
Board Modifications required for use, see Table 2
REF, External Reference
Input
J4 SMA connector
Board Modifications required for use, see Table 1
VCO+, VCO–, External VCO or
Input for clock distribution
Input
J14 and J15 SMA connectors
Board Modifications required to use External VCO.
See Tables 2 and 5. Clock Distribution, see Table 2 only
CPOUT
Output
CPOUT Turret
Used with External VCO, connect to external VCO’s VTUNE
voltage
* These values are for the “LTC6950_PECL0_250MHz” file and the default on board VCO and Reference.
** Any unused RF output must be powered down or terminated with 50Ω, or poor spurious performance may result.



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