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CY2CC1810SC Datasheet(PDF) 3 Page - Cypress Semiconductor

Part # CY2CC1810SC
Description  1:10 Clock Fanout Buffer with Output Enable
PDF  8 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY2CC1810SC Datasheet(HTML) 3 Page - Cypress Semiconductor

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COMLINK™ SERIES
CY2CC1810
Document #: 38-07055 Rev. *C
Page 3 of 8
Power Supply Characteristics (See Figure 1)
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
∆
ICC
Delta ICC Quiescent
Power Supply Current
(IDD @ VDD = Max. and VIN = VDD) – (IDD @ VDD =
Max. and VIN = VDD – 0.6V)
50
uA
ICCD
Dynamic Power Supply
Current
VDD = Max.
Input toggling 50% Duty Cycle,
Outputs Open
fL= fMAX
OE# = VDD
0.63
mA/
MHz
IC
Total Power Supply
Current
VDD = Max.
Input toggling 50% Duty Cycle,
Outputs Open fL = 40 MHz
fL=100 MHz
OE# = GND
25
mA
High-frequency Parametrics
Parameter
Description
Test Conditions
Min.
Typ
Max
Unit
DJ
Jitter, Deterministic
50% duty cycle tW(50–50)
The “point to point load circuit”
|Output Jitter – Input Jitter|
See Figure 8
20
ps
Fmax
Maximum frequency
VDD = 3.3V
50% duty cycle tW(50–50)
Standard Load Circuit.
See Figure 6
160
MHz
50% duty cycle tW(50–50)
The “point to point load circuit”
See Figure 8
200
Fmax(20)
Maximum frequency
VDD = 3.3 V
20% duty cycle tW(20–80)
The “point to point load circuit”
VIN = 3.0V/0.0V VOUT = 2.3V/0.4V
See Figure 8
200
MHz
Maximum frequency
VDD = 2.5 V
The “point to point load circuit”
VIN = 2.4V/0.0V VOUT = 1.7V/0.7V
See Figure 3
100
tW
Minimum pulse
VDD = 3.3 V
The “point to point load circuit”
VIN = 3.0V/0.0V F = 100 MHz
VOUT = 2.0V/0.8V
See Figure 7
2ns
Minimum pulse
VDD = 2.5 V
The “point to point load circuit”
VIN = 2.4V/0.0V F = 100 MHz
VOUT = 1.7V/0.7V
See Figure 2
1
AC Switching Characteristics @ 3.3V VDD = 3.3V ± 5%, TA = –40°C to +85°C (See Figure 6)
Parameter
Description
Min.
Typ.
Max.
Unit
tPLH
Propagation Delay – Low to High
See Figure 9
1.5
3
3.9
nS
tPHL
Propagation Delay – High to Low
1.5
3
3.9
nS
tPHZ
Propagation Delay – High to High Z
See Figure 10
4nS
tPLZ
Propagation Delay – Low to High Z
3
nS
tR
Output Rise Time
See Figure 9
0.8
V/nS
tF
Output Fall Time
0.8
V/nS
tSK(0)
Output Skew: Skew between outputs of the same package (in
phase)
See Figure 12
0.2
nS
tSK(p)
Pulse Skew: Skew between opposite transitions of the same output
(tPHL – tPLH)
See Figure 11
0.2
nS
tSK(t)
Package Skew: Skew between outputs of different packages at the
same power supply voltage, temperature and package type.
See Figure 13
0.3
nS
tOFF
Delay from OE to Driver Off
4.0
nS
tON
Delay from OE to Driver on
4.0
nS



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