TLF6629

June 1989

DM54L72 AND-Gated Master-Slave J-K Flip-Flop

with Preset Clear and Complementary Outputs

General Description

This device contains a positive pulse triggered master-slave

J-K flip-flop with complementary outputs Multiple J and K

inputs are ANDed together to produce the internal J and K

function for the flip-flop The J and K data is processed by

the flip-flop after a complete clock pulse While the clock is

low the slave is isolated from the master On the positive

transition of the clock the data from the AND gates is trans-

ferred to the master While the clock is high the AND gate

inputs are disabled On the negative transition of the clock

the data from the master is transferred to the slave The

logic state of the J and K inputs must not be allowed to

change while the clock is in the high state Data is trans-

ferred to the outputs on the falling edge of the clock pulse

A low logic level on the preset or clear inputs sets or resets

the outputs regardless of the logic levels of the other inputs

Connection Diagram

Dual-In-Line Package

TLF6629 – 1

Order Number DM54L72J or DM54L72W

See NS Package Number J14A or W14B

Function Table

Inputs

Outputs

PR

CLR

CLK

JK

QQ

(Note 1)

(Note 1)

LH

X

X

X

H

L

HL

X

X

X

L

H

LL

X

X

X

H

H

HH

LL

HH

HL

H

L

HH

LH

L

H

HH

H

H

Toggle

Note 1

e

Positive pulse The J and K inputs must be held constant while the

clock is high Data is transferred to the outputs on the falling edge of the

clock pulse

tablished

e

This configuration is nonstable that is it will not persist when the preset

andor clear inputs return to their inactive (high) level

each complete high level clock pulse

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A