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LTM4633

4633f

For more information www.linear.com/LTM4633

applicaTions inForMaTion

PLL, Frequency Synchronization

The LTM4633 device operates up to 750kHz. It can also be

synchronizedwithaninputclockthathasahighlevelabove

2V and a low level below 0.8V at the MODE/PLLIN pin. The

FREQ/PLLLPF pin must be floating when synchronized to

an incoming clock. Once the LTM4633 is synchronized to

an external clock frequency, it will always be running in

forced continuous operation. The synchronizing range is

from 600kHz to 750kHz. For VOUT1,2,3 ≤ 1.5V use 600kHz,

and for VOUT1,2,3 ≥ 1.5V use ≥700kHz. These frequencies

optimize efficiency, eliminate minimum on-time issues

for less than 1V output, and control the inductor ripple

currents over the input and output voltage ranges.

A DC voltage should be applied to the FREQ/PLLLPF pin

to set the operating frequency when clock synchronization

is not used. A voltage divider from the INTVCC pin (5V) to

ground can be used to set the frequency to 600kHz (set

to 1.4V), 700kHz (set to 1.6V), or tie the FREQ/PLLLPF

pin to the INTVCC pin for 750kHz. The top resistor in the

voltage divider should be 50k, and the bottom resistor

should be 19.6k for 600kHz (set to 1.4V), or 23.7k for

700kHz (set to 1.6V). In most cases the FREQ/PLLLPF

pin can be tied to the INTVCC pin for 750kHz operation

as long as the minimum on-time is not below 100ns. See

Figure 18 for an example.

Parallel Channel Operation

For outputs that demand more than 10A of load current,

the LTM4633 device can parallel VOUT1 and VOUT2 to sup-

ply 20A of load current. The two channels will operate at

120° of phase shift. The input RMS ripple current can be

calculated using Equation 1. For example, 12V to 1.2V at

20A equates to duty cycle D = 0.1.

ICIN(RMS) =

20A

0.84

• 0.1• 1– 0.1

(

)

ICIN(RMS) = 7.14ARMS, use 4 × 22µF 16V X5R or X7R

ceramic capacitors rated at 2ARMS each.

The LTM4633 regulators are inherently current mode

controlled devices, so the paralleling of VOUT1 and VOUT2

channels will have good current sharing. This will balance

the thermals in the design. Tie the COMP, VFB, TK/SS

and RUN pins together for these two channels to share

the current evenly. Figure 18 shows a schematic of the

parallel design.

Minimum On-Time

Minimum on-time, tON, is the smallest time duration that

any of the three regulator channels is capable of turning on

the top MOSFET. It is determined by internal timing delays,

and the gate charge required to turn-on the top MOSFET.

Low duty cycle applications may approach this minimum

on-time limit and care should be taken to ensure that:

VOUT

VIN •FREQ

> tON(MIN)

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles.Theoutputvoltagewillcontinuetoberegulated,but

the output ripple and inductor ripple current will increase.

The minimum on-time can be increased by lowering the

switching frequency. A good rule of thumb is to use 100ns

for the minimum on-time.

Output Voltage Tracking

Output voltage tracking can be programmed externally

using the TK/SS pins. The output can be tracked up and

downwithanotherregulator.Themasterregulator’soutput

is divided down with an external resistor divider that is the

same as the slave regulator’s feedback divider to imple-

ment coincident tracking. The LTM4633 uses an accurate

60.4k resistor internally for the top feedback resistor for

each channel. Figure 2 shows an example of coincident

tracking for VOUT1 and VOUT2. VOUT1 is the master and

VOUT2 is the slave:

VSLAVE = 1+

60.4k

RTA

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VTRACK

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