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LTM4608A Datasheet(PDF) 4 Page - Linear Technology |
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LTM4608A Datasheet(HTML) 4 Page - Linear Technology |
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4 / 28 page ![]() LTM4648 4 4648f For more information www.linear.com/LTM4648 elecTrical characTerisTics The l denotes the specifications which apply over the full internal operating temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 5V per typical application. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS GBP Gain Bandwidth Product 3 MHz CMRR Common Mode Rejection (Note 6) 60 dB IDIFFOUT DIFFOUT Current Sourcing 2 mA RIN Input Resistance VOSNS+ to GND 80 kΩ VPGOOD PGOOD Trip Level VFB With Respect to Set Output VFB Ramping Negative VFB Ramping Positive –10 10 % % VPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V INTVCC Linear Regulator VINTVCC Internal VCC Voltage 2.375V ≤ VIN ≤ 5V VIN = 5.5V 4.8 5.15 5 5.25 5.2 5.35 V V VINTVCC Load Reg INTVCC Load Regulation ICC = 0mA to 50mA 0.5 % Oscillator and Phase-Locked Loop fSYNC SYNC Capture Range 250 650 kHz fS Nominal Switching Frequency 400 450 500 kHz RMODE Mode Input Resistance 250 kΩ VIH_CLKIN Clock Input Level High 2.0 V VIL_CLKIN Clock Input Level Low 0.8 V Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Notes are automatically numbered when you apply the note style. Note 2: The LTM4648 is tested under pulsed load conditions such that TJ ≈ TA. The LTM4648E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4648I is guaranteed to meet specifications over the –40°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: The minimum on-time condition is tested at wafer sort. Note 4: See output current derating curves for different VIN, VOUT and TA. Note 5: Guaranteed by design. Note 6: 100% tested at wafer level. |
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