LT8302 datasheet(8/20 Pages) LINER

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LTM8068

8068fb

For more information www.linear.com/LTM8068

PIN FUNCTIONS

VOUT1 (Bank 1): VOUT1 and VOUTN comprise the isolated

output of the LTM8068 flyback stage. Apply an external

capacitor between VOUT1 and VOUTN. Do not allow VOUTN

to exceed VOUT1.

VOUTN (Bank 2): VOUTN is the return for both VOUT1 and

VOUT2. VOUT1 and VOUTN comprise the isolated output of

the LTM8068. In most applications, the bulk of the heat

flow out of the LTM8068 is through the GND and VOUTN

pads, so the printed circuit design has a large impact on

the thermal performance of the part. See the PCB Layout

and Thermal Considerations sections for more details.

Apply an external capacitor between VOUT1 and VOUTN.

VOUT2 (Bank 3): The output of the secondary side linear

post regulator. Apply the load and output capacitor between

VOUT2 and VOUTN. See the Applications Information sec-

tion for more information on output capacitance and

reverse output characteristics.

GND (Bank 4): This is the local ground of the LTM8068

primary. In most applications, the bulk of the heat flow

out of the LTM8068 is through the GND and VOUTN pads,

so the printed circuit design has a large impact on the

thermal performance of the part. See the PCB Layout and

Thermal Considerations sections for more details.

VIN (Bank 5): VIN supplies current to the LTM8068’s inter-

nal regulator and to the integrated power switch. These

pins must be locally bypassed with an external, low ESR

capacitor.

FB2 (Pin A2): This is the input to the error amplifier of the

secondary side LDO post regulator. This pin is internally

clamped to ±7V. The FB2 pin voltage is 1.22V referenced

to VOUTN and the output voltage range is 1.22V to 12V.

Apply a resistor from this pin to VOUTN, using the equation

RFB2 = 608.78/(VOUT2 – 1.22)kΩ. If the post regulator is

not used, leave this pin floating.

BYP (Pin B2): The BYP pin is used to bypass the refer-

ence of the LDO to achieve low noise performance from

the linear post regulator. The BYP pin is clamped internally

to ±0.6V relative to VOUTN. A small capacitor from VOUT2

to this pin will bypass the reference to lower the output

voltage noise. A maximum value of 0.01µF can be used

for reducing output voltage noise to a typical 20µVRMS

over a 100Hz to 100kHz bandwidth. If not used, this pin

must be left unconnected.

RUN (Pin F3): A resistive divider connected to VIN and this

pin programs the minimum voltage at which the LTM8068

will operate. Below 1.24V, the LTM8068 does not deliver

power to the secondary. When RUN is less than 1.24V,

the pin draws 2.5µA, allowing for a programmable hys-

teresis. Do not allow a negative voltage (relative to GND)

on this pin.

FB1 (Pin G7): Apply a resistor from this pin to GND to

set the output voltage VOUT1 relative to VOUTN, using the

recommended value given in Table 1. If Table 1 does not

list the desired VOUT1 value, the equation

RFB1=37.415 VOUT1–0.955

(

)kΩ

may be used to approximate the value. To the seasoned

designer, this exponential equation may seem unusual.

The equation is exponential due to nonlinear current

sources that are used to temperature compensate the

regulation. Do not drive this pin.

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