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LTM8003 Datasheet(PDF) 19 Page - Linear Technology |
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LTM8003 Datasheet(HTML) 19 Page - Linear Technology |
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19 / 26 page ![]() LTM8073 19 8073fa For more information www.linear.com/LTM8073 applicaTions inForMaTion Hot-Plugging Safely The small size, robustness and low impedance of ceramic capacitors make them an attractive option for the input bypass capacitor of LTM8073. However, these capaci- tors can cause problems if the LTM8073 is plugged into a live supply (see Linear Technology Application Note 88 for a complete discussion). The low loss ceramic capacitor combined with stray inductance in series with the power source forms an underdamped tank circuit, and the voltage at the VIN pin of the LTM8073 can ring to more than twice the nominal input voltage, possibly exceeding the LTM8073’s rating and damaging the part. If the input supply is poorly controlled or the LTM8073 is hot-plugged into an energized supply, the input network should be designed to prevent this overshoot. This can be accomplished by installing a small resistor in series to VIN, but the most popular method of controlling input voltage overshoot is add an electrolytic bulk cap to the VIN net. This capacitor’s relatively high equivalent series resistance damps the circuit and eliminates the voltage overshoot. The extra capacitor improves low frequency ripple filtering and can slightly improve the efficiency of the circuit, though it is likely to be the largest component in the circuit. Thermal Considerations The LTM8073 output current may need to be derated if it is required to operate in a high ambient temperature. The amount of current derating is dependent upon the input voltage, output power and ambient temperature. The derating curves given in the Typical Performance Characteristics section can be used as a guide. These curves were generated by the LTM8073 mounted to a 58cm2 4-layer FR4 printed circuit board. Boards of other sizes and layer count can exhibit different thermal behav- ior, so it is incumbent upon the user to verify proper oper- ation over the intended system’s line, load and environ- mental operating conditions. For increased accuracy and fidelity to the actual applica- tion, many designers use FEA (finite element analysis) to predict thermal performance. To that end, Page 2 of the data sheet typically gives four thermal coefficients: θJA – Thermal resistance from junction to ambient θJCbottom – Thermal resistance from junction to the bot- tom of the product case θJCtop – Thermal resistance from junction to top of the product case θJB – Thermal resistance from junction to the printed cir- cuit board. While the meaning of each of these coefficients may seem to be intuitive, JEDEC has defined each to avoid confusion and inconsistency. These definitions are given in JESD 51-12, and are quoted or paraphrased below: θJA is the natural convection junction-to-ambient air ther- mal resistance measured in a one cubic foot sealed enclo- sure. This environment is sometimes referred to as still Figure 3. Layout Showing Suggested External Components, GND Plane and Thermal Vias SYNC GND GND GND GND/THERMAL VIAS SHARE PC RUN VIN CIN FB BIAS AUX RT RFB COUT VOUT RT TR/SS 8073 F03 |
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