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IP2003 Datasheet(PDF) 2 Page - International Rectifier |
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IP2003 Datasheet(HTML) 2 Page - International Rectifier |
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2 / 9 page ![]() www.irf.com 2 iP2003 Measurement were made using four 10uF (TDK C3225X5R1C106KT or equiv.) capacitors across the input (see Fig. 8). Not associated with the rise and fall times. Does not affect Power Loss (see Fig. 9). All specifications @25°C (unless otherwise specified) Absolute Maximum Ratings: Parameter Symbol Min Typ Max Units Conditions VIN to PGND VIN -- 16 V VDD to PGND VDD -- 6.0 V PWM to PGND PWM -0.3 - VDD +0.3 V Not to exceed 6.0V Enable to PGND ENABLE -0.3 - VDD +0.3 V Not to exceed 6.0V Output RMS Current IOUT -- 40 A Measured at VSW Block Temperature TBLK -40 - 125 °C Capable of start up over full temperature range Recommended Operating Conditions: Parameter Symbol Min Typ Max Units Conditions Supply Voltage VDD 4.6 5.0 5.5 V Input Voltage VIN 3.0 - 13.2 V Output Voltage VOUT 0.8 - 3.3 V Output Current IOUT -- 40 A Operating Frequency fsw 300 - 1000 kHz Operating Duty Cycle D - - 85 % Electrical Specifications @ VDD = 5V (unless otherwise specified): Parameter Symbol Min Typ Max Units Conditions Block Power Loss c PLOSS - 9.4 11.7 W VIN=12V, VOUT=1.3V Turn On Delay d td(on) -63- IOUT=40A, fSW=1MHz Turn Off Delay d td(off) -26 - L = 0.3µH VIN Quiescent Current IQ-VIN -- 1.0 mA Enable = 0V, VIN=12V VDD Quiescent Current IQ-VDD -10 - µA Enable = 0V, VDD=5V Under-Voltage Lockout UVLO Start Threshold VSTART 4.2 4.4 4.5 V Hysteresis VHvs-UVLO -150 - mV Enable ENABLE Input Voltage High VIH 2.0 - - V Input Voltage Low VIL -- 0.8 Power Ready PRDY Logic Level High VOH 4.5 4.6 - V VDD=4.6V, ILoad=10mA Logic Level Low VOL -0.1 0.2 VDD <UVLO Threshold, ILoad = 1mA PWM Input PWM Logic Level High VOH 2.0 - - V Logic Level Low VOL -- 0.8 ns |
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