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LT3668

3668fa

For more information www.linear.com/LT3668

APPLICATIONS INFORMATION

PCB Layout

For proper operation and minimum EMI, care must be

taken during printed circuit board layout. Figure 8 shows

the recommended component placement with trace,

ground plane and via locations. Note that large, switched

currents flow in the LT3668’s IN1, SW, GND and DA pins,

thecatchdiodeandtheinputcapacitor.Theloopformedby

these components should be as small as possible. These

components,alongwiththeinductorandoutputcapacitor,

should be placed on the same side of the circuit board,

and their connections should be made on that layer. Place

a local, unbroken ground plane below these components.

The SW and BOOST nodes should be as small as possible.

Keep the FB1 node small so that the ground traces will

shield it from the SW and BOOST nodes. The exposed pad

must be soldered such that it can act as a heat sink. (See

High Temperature Considerations section.)

Hot Plugging Safely

The small size, robustness and low impedance of ceramic

capacitors make them an attractive option for the input

bypass capacitors of LT3668 circuits. However, these ca-

pacitors can cause problems if the LT3668 is plugged into

a live supply. The low loss ceramic capacitor, combined

with stray inductance in series with the power source,

forms an under damped tank circuit, and the voltage at the

input pins of the LT3668 can ring to twice their nominal

input voltage, possibly exceeding the LT3668’s rating and

damaging the part. If the input supply is poorly controlled

or the user will be plugging the LT3668 into an energized

supply, the input network should be designed to prevent

thisovershoot.SeeLinearTechnologyApplicationNote 88

for a complete discussion.

High Temperature Considerations

The LT3668’s maximum rated junction temperature of

125°C (E- and I-grade) and 150oC (H-grade), respectively,

limits its power handling capability.

Power dissipation within the switching regulator can be

estimated by calculating the total power loss from an

efficiency measurement and subtracting inductor loss.

Be aware that at high ambient temperatures the external

Schottky diode will have significant leakage current (see

Typical Performance Characteristics), increasing the qui-

escent current of the switching regulator.

The power dissipation of each LDO is comprised of two

components. Each power device dissipates:

PPASS = (VIN − VOUT) • IOUT

where PPASS is the power, VIN the input voltage, VOUT

the output voltage, and IOUT the output current. The base

currents of the LDO power PNP transistors flow to ground

internally and are the major component of the ground

current. For each LDO, this causes a power dissipation

PGND of:

PGND = VIN • IGND

where VIN is the input voltage and IGND the ground current

generated by the corresponding power device. GND pin

Figure 8. Good PCB Layout Ensures Proper,

Low EMI Operation

IN1

GND

OUT1

VIAS TO LOCAL GROUND PLANE

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