LT6237 datasheet(5/22 Pages) LINER

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LTC2312-12

231212fa

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aDc TiMing characTerisTics

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

fSAMPLE(MAX) Maximum Sampling Frequency

(Notes 7, 8)

500

kHz

fSCK

Shift Clock Frequency

(Notes 7, 8)

MHz

tSCK

Shift Clock Period

tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV

2000

tCONV

Conversion Time

1400

tACQ

Acquisition Time

600

Minimum CONV Pulse Width

(Note 7), Valid for Nap and Sleep Modes Only

SCK↑ Setup Time After CONV↓

(Note 7), Valid for Nap and Sleep Modes Only

SDO Enable Time After CONV↓

(Notes 7, 8)

SDO Data Valid Access Time after SCK↓

(Notes 7, 8, 9)

SCK Low Time

SCK High Time

SDO Data Valid Hold Time After SCK↓

(Notes 7, 8, 9)

SDO into Hi-Z State Time After CONV↑

(Notes 7, 8, 10)

CONV↑ Quiet Time After 12th SCK↓

(Note 7)

tWAKE_NAP

Power-Up Time from Nap Mode

See Nap Mode Section

tWAKE_SLEEP Power-Up Time from Sleep Mode

See Sleep Mode Section

1.1

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. (Note 4)

Note 1. Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2. All voltage values are with respect to ground.

Note 3. When these pin voltages are taken below ground or above VDD

(AIN, REF) or OVDD (SCK, CONV, SDO) they will be clamped by internal

diodes. This product can handle input currents up to 100mA below ground

or above VDD or OVDD without latch-up.

Note 4. VDD = 5V, OVDD = 2.5V, fSMPL = 500kHz, fSCK = 20MHz,

AIN = –1dBFS and internal reference unless otherwise noted.

Note 5. Integral nonlinearity is defined as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 6. Typical RMS noise at code transitions.

Note 7. Parameter tested and guaranteed at OVDD = 2.5V. All input signals

are specified with tr = tf = 1ns (10% to 90% of OVDD) and timed from a

voltage level of OVDD/2.

Note 8. All timing specifications given are with a 10pF capacitance load.

Load capacitances greater than this will require a digital buffer.

Note 9. The time required for the output to cross the VOH or VOL voltage.

Note 10. Guaranteed by design, not subject to test.

Note 11. Recommended operating conditions.

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