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LTC2358-16

Rev A

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converter on initial power-up and whenever VDD drops

below 2V. Once the supply voltage re-enters the nominal

supply voltage range, the POR reinitializes the ADC. No

conversions should be initiated until at least 10ms after

a POR event to ensure the initialization period has ended.

Whenemployingtheinternalreferencebuffer,allow200ms

forthebuffertopowerupandrechargetheREFBUFbypass

capacitor. Any conversion initiated before these times will

produce invalid results.

TIMING AND CONTROL

CNV Timing

The LTC2358-16 sampling and conversion is controlled

by CNV. A rising edge on CNV transitions all channels’ S/H

circuits from track mode to hold mode, simultaneously

sampling the input signals on all channels and initiating

a conversion. Once a conversion has been started, it

cannot be terminated early except by resetting the ADC,

as discussed in the Reset Timing section. For optimum

performance, drive CNV with a clean, low jitter signal and

avoid transitions on data I/O lines leading up to the rising

edge of CNV. Additionally, to minimize channel-to-channel

crosstalk, avoid high slew rates on the analog inputs for

100ns before and after the rising edge of CNV. Converter

status is indicated by the BUSY output, which transitions

low-to-high at the start of each conversion and stays high

untiltheconversioniscomplete.OnceCNVisbroughthigh

to begin a conversion, it should be returned low between

40ns and 60ns later or after the falling edge of BUSY to

minimizeexternaldisturbancesduringtheinternalconver-

sion process. The CNV timing required to take advantage

of the reduced power nap mode of operation is described

in the Nap Mode section.

Internal Conversion Clock

The LTC2358-16 has an internal clock that is trimmed to

achieve a maximum conversion time of 550•N ns with N

channels enabled. With a minimum acquisition time of

570ns when converting eight channels simultaneously,

throughputperformanceof200kspsisguaranteedwithout

any external adjustments. Also note that the minimum

acquisition time varies with sampling frequency (fSMPL)

and the number of enabled channels.

Nap Mode

The LTC2358-16 can be placed into nap mode after a con-

versionhasbeencompletedtoreducepowerconsumption

between conversions. In this mode a portion of the device

circuitry is turned off, including circuits associated with

sampling the analog input signals. Nap mode is enabled

by keeping CNV high between conversions, as shown in

Figure 13. To initiate a new conversion after entering nap

mode, bring CNV low and hold for at least 750ns before

bringingithighagain.Theconverteracquisitiontime(tACQ)

is set by the CNV low time (tCNVL) when using nap mode.

Power Down Mode

When PD is brought high, the LTC2358-16 is powered

down and subsequent conversion requests are ignored. If

this occurs during a conversion, the device powers down

once the conversion completes. In this mode, the device

APPLICATIONS INFORMATION

CNV

tCONV

tACQ

BUSY

NAP

NAP MODE

tCNVL

235816 F13

Figure 13. Nap Mode Timing for the LTC2358-16

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