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LTC2862A

2862af

For more information www.linear.com/LTC2862A

applicaTions inForMaTion

Enhanced EOS Protection

The improved ESD protection of the LTC2862A also pro-

vides superior resistance to electrical overstress (EOS)

damageinthepresenceoflargefaultvoltagesappliedfrom

low impedance faults. The LTC2862A employs thyristor

type ESD protection on the A, B pins. While thyristors have

the low on-state impedance and high robustness needed

to achieve the very high levels of ESD protection of the

LTC2862A, they have the disadvantage of snapping back

to a low voltage conduction state after they have been

triggered by an initial voltage that exceeds ~±80V. In the

presence of a high voltage, high current fault source, the

large resulting currents will blow the bond wires inside

the LTC2862A package, resulting in a failed chip.

TheLTC2862Amitigatestheprobabilityofthistypeoffailure

by establishing a very high trigger current in addition to a

higher trigger voltage. In order to trigger the ESD cell, the

fault must not only exceed the ~±80V trigger voltage, but

must be able to source ~±500mA at that voltage to initiate

the snapback of the ESD cell. This makes the LTC2862A

muchlesssusceptibletosnapbackinducedfailurescreated

by high voltage noise spikes or voltage transients caused

by inductive overshoot when the A,B pins are shorted to a

fault voltage source. (The snapback characteristics of the

ESD protection are not tested during production.)

Driver

ThedriverprovidesfullRS485/RS422compatibility.When

enabled, if DI is high, A–B is positive. When the driver is

disabled, both transmitter outputs are high impedance,

and the impedance is dominated by the receiver input

resistance, RIN.

Driver Overvoltage and Overcurrent Protection

The driver outputs are protected from short circuits to any

voltage within the Absolute Maximum range of –60V to

60V. The maximum current in a fault condition is ±250mA.

The driver includes a progressive foldback current limiting

circuit that continuously reduces the driver current limit

with increasing output fault voltage. The fault current is

less than ±15mA for fault voltages over ±40V.

All devices also feature thermal shutdown protection that

disables the driver and receiver in case of excessive power

dissipation (see Note 4). (Thermal shutdown is not tested

during production.)

Full Failsafe Operation

Whentheabsolutevalueofthedifferentialvoltagebetween

the A and B pins is greater than 200mV with the receiver

enabled, the state of RO will reflect the polarity of (A–B).

These parts have a failsafe feature that guarantees the

receiveroutputwillbeinalogic1state(theidlestate)when

the inputs are shorted, left open, or terminated but not

driven. The delay allows normal data signals to transition

through the threshold region without being interpreted as

a failsafe condition. This failsafe feature is guaranteed to

work for inputs spanning the entire common mode range

of –25V to 25V.

Most competing devices achieve the failsafe function by a

simple negative offset of the input threshold voltage. This

causes the receiver to interpret a zero differential voltage

as a logic 1 state. The disadvantage of this approach is

the input offset can introduce duty cycle asymmetry at the

receiver output that becomes increasingly worse with low

input signal levels and slow input edge rates.

Other competing devices use internal biasing resistors to

create a positive bias at the receiver inputs in the absence

of an external signal. This type of failsafe biasing is

ineffectiveifthenetworklinesareshorted,orifthenetwork

is terminated but not driven by an active transmitter.

Figure 9. Duty Cycle of Balanced Receiver with ±200mV

10Mbps Input Signal

A, B

200mV/DIV

A–B

200mV/DIV

40ns/DIV

286A F08

1.6V/DIV

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