LTC2858 datasheet(18/32 Pages) LINER

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LTC2876/LTC2877

28767fa

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applicaTions inForMaTion

glitches resulting from receiver inputs that momentarily

cross into the region between the signal rising and falling

thresholds as illustrated in Figure 14, event 3.

SHUTDOWN MODE DELAY

The LTC2876 and LTC2877 feature a low power shutdown

mode that is entered when both the driver and receiver

are simultaneously disabled (pin DE low and RE high).

A shutdown mode delay of approximately 250ns (not

tested in production) is imposed after the state is received

before the chip enters shutdown. If either DE goes high

or RE goes low during this delay, the delay timer is reset

and the chip does not enter shutdown. This reduces the

chance of accidentally entering shutdown if DE and RE are

driven in parallel by a slowly changing signal or if DE and

RE are driven by two independent signals with a timing

skew between them.

This shutdown mode delay does not affect the outputs of

the transmitter and receiver, which start to switch to the

highimpedancestateuponthereceptionoftheirrespective

disable signals as defined by the parameters tSHDND and

tSHDNR. The shutdown mode delay affects only the time

when all the internal circuits that draw DC power from

VCC are turned off.

POWER-UP/DOWN GLITCH-FREE OUTPUTS

TheLTC2876andLTC2877employanundervoltagedetec-

tioncircuittocontroltheactivationoftheon-chipcircuitry.

During power-up, PB, PA, and RO are undriven, until the

VCC supply reaches a voltage sufficient to reliably operate

the chip. In this mode, only the internal pull-up resistor

on RO and the receiver input resistance to ground on PA

and PB offer weak conduction paths at those pins. As the

supplyvoltagerisesabovetheundervoltagethreshold,and

if the device is configured for drive mode, the PB and PA

pins become active and are driven to a state that reflects

the input condition on DI. Likewise, if the device is config-

ured for receive mode, the RO pin is driven high or low to

reflect the state of the differential voltage across PB–PA.

During power down, the reverse occurs; the supply un-

dervoltage detection circuit senses low supply voltage

and immediately puts the chip into shutdown. The driver

and receiver outputs go to the undriven state. RO is pulled

up through the internal 250k pull-up resistor and PA, PB

are pulled low through the 125k receiver input resistors.

If the LTC2876/LTC2877 is powered or depowered when

configured for shutdown (RE = 0V and DE = VL (LTC2877)

or VCC (LTC2876) then RO, PB, and PA will remain in the

undriven state, without glitching high or low during the

supply transition. This allows the powering and depower-

ing of the LTC2876/LTC2877 when connected onto a live

network without disturbing the lines.

Figure 13. The LTC2876/LTC2877 Signal Thresholds (VTS–, VTS+)

and Failsafe Thresholds (VTFS–, VTFS+)

(PB–PA)

28767 F13

–200mV

+200mV

–75mV

–120mV

+120mV

∆VTS

VTS–,VTFS– VTFS+

VTS+

∆VTFS

Figure 14. LTC2876/LTC2877 Receiver Operation. Event 1: Signal

Rises into Region Between Signal Thresholds, Resulting in the

RO Transitioning to a Failsafe Condition After a Fixed Delay of

About 1.5µs. Event 2: Input Signal Falls Below Negative Signal

Threshold, Resulting in an Immediate Fall on RO. Event 3:

Signal Glitches into the Region Between Signal Thresholds for a

Period Less Than the Failsafe Delay Time (~1.5µs), Resulting in

an Unchanged Output. Event 4: Signal Transitions Above Rising

Signal Threshold, Resulting in an Immediate Rise in RO

+200mV

–200mV

VTS+

VTFS+

VTS–, VTFS–

–120mV

+120mV

(PB–PA)

–75mV

28767 F14

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