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LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

circuitry is turned off, including circuits associated with

sampling the analog input signals. Nap mode is enabled

by keeping CNV high between conversions, as shown in

Figure 14. To initiate a new conversion after entering nap

mode, bring CNV low and hold for at least 420ns before

bringingithighagain.Theconverteracquisitiontime(tACQ)

is set by the CNV low time (tCNVL) when using nap mode.

Power Down Mode

When PD is brought high, the LTC2335-18 is powered

down and subsequent conversion requests are ignored. If

this occurs during a conversion, the device powers down

once the conversion completes. In this mode, the device

draws only a small regulator standby current resulting in a

typical power dissipation of 0.36mW. To exit power down

mode, bring the PD pin low and wait at least 10ms before

initiating a conversion. When employing the internal refer-

ence buffer, allow 200ms for the buffer to power up and

recharge the REFBUF bypass capacitor. Any conversion

initiated before these times will produce invalid results.

applicaTions inForMaTion

Reset Timing

A global reset of the LTC2335-18, equivalent to a power-

on-reset event, may be executed without needing to cycle

the supplies. This feature is useful when recovering from

system-level events that require the state of the entire sys-

tem to be reset to a known synchronized value. To initiate

a global reset, bring PD high twice without an intervening

conversion, as shown in Figure 15. The reset event is trig-

geredonthesecondrisingedgeofPD,andasynchronously

ends based on an internal timer. Reset clears all serial data

outputregistersandrestorestheinternalsequencerdefault

state of converting channels 0 through 7 sequentially, all

in SoftSpan 7. If reset is triggered during a conversion, the

conversion is immediately halted. The normal power down

behavior associated with PD going high is not affected by

reset. Once PD is brought low, wait at least 10ms before

initiating a conversion. When employing the internal refer-

ence buffer, allow 200ms for the buffer to power up and

recharge the REFBUF bypass capacitor. Any conversion

initiated before these times will produce invalid results.

Figure 15. Reset Timing for the LTC2335-18

CNV

tCONV

tCNVH

tPDH

tPDL

BUSY

RESET

RESET TIME

SET INTERNALLY

SECOND RISING EDGE OF

PD TRIGGERS RESET

tWAKE

233518 F15

Figure 14. Nap Mode Timing for the LTC2335-18

CNV

tCONV

tACQ

BUSY

NAP

NAP MODE

tCNVL

233518 F14

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