LTC2345-16

34

234516f

For more information www.linear.com/LTC2345-16

channels 0 and 1, 2 and 3, 4 and 5, and 6 and 7, respec-

tively,usingfouroutputlanes.Similarly,capturingthefirst

four packets (96 SCKI cycles total) from SDO0 and SDO4

provides data for analog input channels 0 to 3 and 4 to

7, respectively, using two output lanes. If only one lane

can be accommodated, capturing the first eight packets

(192 SCKI cycles total) from SDO0 provides data for all

analog input channels. As shown in Table 3, full 200ksps

per channel throughput can be achieved with a 90MHz

SCKI frequency in the four lane case, but the maximum

CMOS SCKI frequency of 100MHz limits the throughput

to less than 200ksps per channel in the two lane and one

lane cases. Finally, note that in choosing the number of

lanes and which lanes to use for data capture, the user is

notrestrictedtothespecificcasesmentionedabove.Other

choices may be more optimal in particular applications.

Programming the SoftSpan Configuration Register in

CMOS I/O Mode

The internal 24-bit SoftSpan configuration register con-

trols the SoftSpan range for all analog input channels of

the LTC2345-16. The default state of this register after

power-up or resetting the device is all ones, configuring

(see Table 1a). The state of this register may be modified

by providing a new 24-bit SoftSpan configuration word on

SDI during the data transaction window shown in Figure

17. New SoftSpan configuration words are only accepted

within this recommended data transaction window, but

SoftSpan changes take effect immediately with no addi-

tional analog input settling time required before starting

the next conversion. Setting a channel’s SoftSpan code to

SS[2:0] = 000 immediately disables the channel, resulting

sion. Similarly, enabling a previously disabled channel

requires no additional analog input settling time before

starting the next conversion. The mapping between the

serial SoftSpan configuration word, the internal SoftSpan

configuration register, and each channel’s 3-bit SoftSpan

code is illustrated in Figure 19.

If fewer than 24 SCKI rising edges are provided during a

data transaction window, the partial word received on SDI

willbeignoredandtheSoftSpanconfigurationregisterwill

notbeupdated.Ifexactly24SCKIrisingedgesareprovided,

the SoftSpan configuration register will be updated to

match the received SoftSpan configuration word, S[23:0].

The one exception to this behavior occurs when S[23:0] is

all zeros. In this case, the SoftSpan configuration register

will not be updated, allowing applications to retain the

current SoftSpan configuration state by idling SDI low. If

more than 24 SCKI rising edges are provided during a data

transaction window, each complete 24-bit word received

on SDI will be interpreted as a new SoftSpan configuration

word and applied to the SoftSpan configuration register

as described above. Any partial words are ignored.

Typically, applications will update the SoftSpan configura-

tion register in the manner shown in Figures 17 and 18.

After the opening of a new data transaction window at the

falling edge of BUSY, the user supplies a 24-bit SoftSpan

configuration word on SDI during the first 24 SCKI cycles.

Thisnewwordoverwritestheinternalconfigurationregister

applicaTions inForMaTion

Table 3. Required SCKI Frequency to Achieve Various Throughputs in Common Output Bus Configurations with Eight Channels

I/O MODE

NUMBER OF SDO

LANES

NUMBER OF SCKI

CYCLES

200ksps/CHANNEL

100ksps/CHANNEL

50ksps/CHANNEL

CMOS

8

16

30

3

2

8

24

45

5

2

4

48

90

9

4

2

96

Not Achievable

18

7

1

192

Not Achievable

35

13

LVDS

1

96

180 (360Mbps)

18 (36Mbps)

7 (14Mbps)