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LTC2345-18

234518f

For more information www.linear.com/LTC2345-18

applicaTions inForMaTion

OVERVIEW

The LTC2345-18 is an 18-bit, low noise 8-channel si-

multaneous sampling successive approximation register

(SAR) ADC with differential, wide common mode range

inputs. Using the integrated low-drift reference and buffer

(VREFBUF = 4.096Vnominal),eachchannelofthisSoftSpan

ADC can be independently configured on a conversion-

by-conversion basis to accept ±4.096V, 0V to 4.096V,

±2.048V, or 0V to 2.048V signals. The input signal range

may be expanded up to ±5V using an external 5V refer-

ence. Individual channels may also be disabled to increase

throughput on the remaining channels.

The wide input common mode range and high CMRR

(102dB typical, VIN+ = VIN– = 3.6VP-P 200Hz Sine) of the

LTC2345-18 analog inputs allow the ADC to directly digi-

tize a variety of signals, simplifying signal chain design.

This input signal flexibility, combined with ±5LSB INL,

no missing codes at 18-bits, and 91.8dB SNR, makes

the LTC2345-18 an ideal choice for many applications

requiring wide dynamic range.

The LTC2345-18 supports pin-selectable SPI CMOS (1.8V

to 5V) and LVDS serial interfaces, enabling it to com-

municate equally well with legacy microcontrollers and

modern FPGAs. In CMOS mode, applications may employ

between one and eight lanes of serial output data, allowing

the user to optimize bus width and data throughput. The

LTC2345-18 typically dissipates 81mW when converting

eight analog input channels simultaneously at 200ksps

per channel throughput. An optional power-down mode

may be employed to further reduce power consumption

during inactive periods.

CONVERTER OPERATION

The LTC2345-18 operates in two phases. During the ac-

quisition phase, the sampling capacitors in each channel’s

sample-and-hold (S/H) circuit connect to their respective

analog input pins and track the differential analog input

voltage (VIN+ – VIN–). A rising edge on the CNV pin transi-

tions all channels’ S/H circuits from track mode to hold

mode, simultaneously sampling the input signals on all

channelsandinitiatingaconversion.Duringtheconversion

phase, each channel’s sampling capacitors are connected,

one channel at a time, to an 18-bit charge redistribution

capacitor D/A converter (CDAC). The CDAC is sequenced

throughasuccessiveapproximationalgorithm,effectively

comparingthesampledinputvoltagewithbinary-weighted

fractions of the channel’s SoftSpan full-scale range (e.g.,

VFSR/2, VFSR/4 … VFSR/262144) using a differential

comparator. At the end of this process, the CDAC output

approximates the channel’s sampled analog input. Once

all channels have been converted in this manner, the ADC

control logic prepares the 18-bit digital output codes from

each channel for serial transfer.

TRANSFER FUNCTION

TheLTC2345-18digitizeseachchannel’sfull-scalevoltage

range into 218 levels. In conjunction with the ADC master

reference voltage, VREFBUF, a channel’s SoftSpan configu-

ration determines its input voltage range, full-scale range,

LSB size, and the binary format of its conversion result, as

shown in Tables 1a and 1b. For example, employing the

internal reference and buffer (VREFBUF = 4.096V nominal),

SoftSpan 7 configures a channel to accept a ±4.096V bi-

polar analog input voltage range, which corresponds to a

8.192Vfull-scalerangewitha31.25μVLSB.OtherSoftSpan

configurationsandreferencevoltagesmaybeemployedto

convert both larger and smaller bipolar and unipolar input

ranges. Conversion results are output in two’s comple-

ment binary format for all bipolar SoftSpan ranges, and

in straight binary format for all unipolar SoftSpan ranges.

The ideal two’s complement transfer function is shown in

Figure 2, while the ideal straight binary transfer function

is shown in Figure 3.

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