LTC4301L datasheet(10/20 Pages) LINER

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LTC4312

4312f

APPLICATIONS INFORMATION

Figure 3. Connection of the LTC4312 in a Level Shift Application. VCC2 Is

Less Than or Equal to the Minimum Bus Supply Voltage on the Output Side

If VCC2 is tied low, the output side rise time accelerators

are disabled independent of the state of the ACC pin.

ACC tied high disables input and output RTAs. Using a

combination of the ACC pin and the VCC2 voltage allows

the user independent control of the input and output side

rise time accelerators. The rise time accelerators are also

internally disabled during power-up and VCC2 transitions,

as described in the Operation section, as well as during

automatic clocking and stop bit generation for a bus stuck

low recovery event.

The rise time accelerators when activated pull the bus up

to 0.9•VCC on the input side of the SDA and SCL lines.

On the output side the SDAOUT and SCLOUT lines are

pulled up by the rise time accelerators to 0.8•VCC2. For

VCC2 voltages approaching 2.3V, acceleration of the output

bus may not be seen all the way to 0.8•VCC2 due to the

threshold voltage of the NFET pass device.

Supply Voltage Considerations in Level Translation

Applications

Care must be taken to ensure that the bus supply voltages

on the input and output sides are greater than 0.9•VCC and

0.8•VCC2, respectively, to ensure that the bus is not driven

above the bus supplies by the rise time accelerators. This

is usually accomplished in a level shifting application by

tying VCC to the input bus supply and VCC2 to the minimum

bus supply on the output side as shown in Figure 3.

If VCC2isgrounded,themultiplexerpassgatesarepowered

from VCC. In this case the minimum output bus supply

of the enabled channels should be greater than or equal

to VCC to prevent cross-conduction between the enabled

output channels. This is shown in Figure 4. Grounding VCC2

as shown in Figure 4 disables the output side rise time

accelerators independent of the state of the ACC pin. The

input rise time accelerators in this conﬁguration continue

to be controlled by the ACC pin and can be enabled inde-

pendently. In Figure 4, ACC is left open to obtain a high VIL

and a 3mA rise time accelerator current on the input side.

LTC4312

GND

VCC

VCC2

4312 F03

SCLOUT1

SDAOUT1

SCLOUT2

SDAOUT2

SCLOUT1

SDAOUT1

SCLOUT2

SDAOUT2

SCLIN

SDAIN

ENABLE1

ENABLE2

ACC

DISCEN

FAULT

SCLIN

SDAIN

ENABLE1

ENABLE2

3.3V

FAULT

10k

0.01μF

3.3V

10k

0.01μF

10k

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