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LTC4312 Datasheet(PDF) 1 Page - Linear Technology

Part # LTC4312
Description  Dual I2C/SMBus Address Translator
PDF  16 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC4312 Datasheet(HTML) 1 Page - Linear Technology

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LTC4318
1
4318fa
For more information www.linear.com/LTC4318
Typical applicaTion
FeaTures
DescripTion
Dual I2C/SMBus
Address Translator
The LTC®4318 enables the hardwired address of one or
more I2C or SMBus slave devices to be translated to a
different address. This allows slaves with the same hard-
wired address to coexist on the same bus. Only discrete
resistors are needed to select the new address and no
software programming is required. Up to 127 different
address translations are available.
The LTC4318 incorporates a pass-through mode which
disables the address translations and allows general call
addressing by the master. The LTC4318 is designed to
automatically recover from abnormal bus conditions like
bus stuck low or premature STOP bits.
PART NUMBER
NUMBER OF INPUT
CHANNELS
NUMBER OF OUTPUT
CHANNELS
LTC4316
1
1
LTC4317
1
2
LTC4318
2
2
applicaTions
n
Allows Multiple Slaves with the Same Address to
Coexist on the Same Bus
n
Resistor Configurable Address Translation
n
No Software Programming Required
n
Compatible with SMBus, I2C and I2C Fast Mode
n
Pass-Through Mode Allows General Call Addressing
n
±4kV HBM ESD Ruggedness
n
Level Translation for 2.5V, 3.3V and 5V Buses
n
Stuck Bus Timeout
n
Prevents SDA and SCL Corruption During Live Board
Insertion and Removal
n
Support Bus Hot Swap
n
20-Lead QFN 4mm × 4mm Package
n
I2C, SMBus Address Expansion
n
Address Translation
n
Servers
n
Telecom
L
, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 6356140, 6650174, 7032051, 7478286. Patent pending.
SCL
SDA
4318 TA01a
3.3V
845k
61.9k
3.3V
3.3V
MASTER #1
SCLOUT1
SDAOUT1
READY1
SCLIN1
SDAIN1
SCLIN2
SDAIN2
ENABLE1
SENDS
ADDRESS 0x34
SCL
SDA
5V
SLAVE# 1
RECEIVES
ADDRESS 0X36
TRANSLATES
BY 0x04
TRANSLATES
BY 0x02
XORL1
XORL2
LTC4318
VCC
GND
ENABLE2 READY2
93.1k
SCL
SDA
MASTER #1
SENDS
ADDRESS 0x32
SCLOUT2
SDAOUT2
XORH2
XORH1
SCL
SDA
5V
SLAVE# 2
RECEIVES
ADDRESS 0X36
4318 TA01b
TRANSLATION
BYTE
SDAOUT1
SCLIN1
SDAIN1
ADDRESS BITS
START
a6
a5
a4
a3
a2
a1
a0
0
1
1
0
1
0
0
= 0x34
0
0
0
0
0
1
0
= 0x02
0
0
0
0
1
1
0
1
1
0
= 0x36
R/W
BIT
ACK
BIT


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