CA3083 datasheet(2/4 Pages) RENESAS

2 / 4 page

CA-3083

FN481 Rev.7.00

Page 2 of 4

December 15, 2011

Absolute Maximum Ratings

Thermal Information

The following ratings apply for each transistor in the device:

Collector-to-Emitter Voltage, VCEO . . . . . . . . . . . . . . . . . . . . . . 15V

Collector-to-Base Voltage, VCBO. . . . . . . . . . . . . . . . . . . . . . . . 20V

Collector-to-Substrate Voltage, VCIO (Note 1). . . . . . . . . . . . . . 20V

Emitter-to-Base Voltage, VEBO . . . . . . . . . . . . . . . . . . . . . . . . . . 5V

Collector Current (IC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA

Base Current (IB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA

Operating Conditions

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to 125°C

Thermal Resistance (Typical, Note 2)

JA (°C/W) JC (°C/W)

PDIP Package . . . . . . . . . . . . . . . . . . .

135

N/A

SOIC Package . . . . . . . . . . . . . . . . . . .

200

N/A

Maximum Power Dissipation (Any One Transistor) . . . . . . . 500mW

Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C

Maximum Storage Temperature Range . . . . . . . . . -65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. The collector of each transistor of the CA3083 is isolated from the substrate by an integral diode. The substrate must be connected to a voltage

which is more negative than any collector voltage in order to maintain isolation between transistors and provide normal transistor action. To

avoid undesired coupling between transistors, the substrate Terminal (5) should be maintained at either DC or signal (AC) ground. A suitable

bypass capacitor can be used to establish a signal ground.

JA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

For Equipment Design, TA = 25°C

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

FOR EACH TRANSISTOR

Collector-to-Base Breakdown Voltage

V(BR)CBO

IC = 100A, IE = 0

Collector-to-Emitter Breakdown Voltage

V(BR)CEO

IC = 1mA, IB = 0

Collector-to-Substrate Breakdown Voltage

V(BR)CIO

ICI = 100A, IB = 0, IE = 0

Emitter-to-Base Breakdown Voltage

V(BR)EBO

IE = 500A, IC = 0

6.9

Collector-Cutoff-Current

ICEO

VCE = 10V, IB = 0

A

Collector-Cutoff-Current

ICBO

VCB = 10V, IE = 0

A

DC Forward-Current Transfer Ratio (Note 3) (Figure 1)

hFE

VCE = 3V

IC = 10mA

IC = 50mA

Base-to-Emitter Voltage (Figure 2)

VBE

VCE = 3V, IC = 10mA

0.65

0.74

0.85

Collector-to-Emitter Saturation Voltage (Figures 3, 4)

VCE SAT

IC = 50mA, IB = 5mA

0.40

0.70

Gain Bandwidth Product

VCE = 3V, IC = 10mA

450

MHz

FOR TRANSISTORS Q1 AND Q2 (As a Differential Amplifier)

Absolute Input Offset Voltage (Figure 6)

|VIO|VCE = 3V, IC = 1mA

1.2

Absolute Input Offset Current (Figure 7)

|IIO|VCE = 3V, IC = 1mA

0.7

2.5

A

NOTE:

3. Actual forcing current is via the emitter for this test.

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