11/15

L8202

9

VOLTAGE SUPERVISOR

nRESET is an Output/Input signal (active low), that is used both to provide the information about the status

of Vcc and Vs supplies, both to provide a Reset signal to the internal logic when driven "low" from an ex-

ternal source for a period > 30

µs.

When nRESET is asserted, Motor Drivers and VDD regulator are forced in the inactive state and the Serial

Input Port is loaded with the "Reset Value".

To avoid false assertion due to glitches, nRESET is released to the "high" state with a delay of 100ms.

Delay period is calculated from the moment Vcc is passing the Vcc threshold.

At power down no delay is present, and nRESET is asserted low by Vcc or Vs falling low respect to their

thresholds

Figure 5.

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Vout_high

High-level output voltage at

nRESET

Ioh = -0.1 mA

Vcc-

0.5V

V

Vout_low

Low-level output voltage at

nRESET

Vs=38V

0.2

V

Rp_up

Internal pull-up resistance

between Vcc_in and nRESET

23

5

K

Ω

Threshold voltage at Vcc &

Vcc_in

Vcc = 3.3V

Vcc_in = 3.3V

2.87

2.82

3.07

3.10

V

Vcc = 5.0V

Vcc_in = 3.3V

4.35

2.87

4.65

3.10

Low threshold voltage at Vs

Vcc > VTH_VCC

Vs decreasing

18.0

20.0

V

High threshold voltage at Vs

Vcc > VTH_VCC

Vs increasing

19.25

21.25

V

Hysteresis Voltage

V

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Td

nRESET delay

70

100

130

ms

Tdeglitch

Vcc out of tolerance

persistence time

nRESET deasserted

10

20

30

µs

Trise

Rise Time at nRESET

10 to 90%, 50pF Load

750

ns

Tfall

Fall Time at nRESET

90 to 10%, 50pF Load

50

ns

Td

Td

Tdeglitch

Vs

Vcc

nRESET

Note A. L8202 ignores very brief transients.

This should be less than Tdeglitch

A

Td

Td

Tdeglitch

Vs

Vcc

nRESET

Note A. L8202 ignores very brief transients.

This should be less than Tdeglitch

A