| Electronic Components Datasheet Search |
|
EL7554IREZ Datasheet(PDF) 13 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
EL7554IREZ Datasheet(HTML) 13 Page - Renesas Technology Corp |
|
13 / 14 page ![]() FN7360 Rev 5.00 Page 13 of 14 November 5, 2007 EL7554 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2004-2007. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Thermal Management The EL7554IRE is packaged in a thermally-efficient HTSSOP-28 package, which utilizes the exposed thermal pad at the bottom to spread heat through PCB metal. Therefore: 1. The thermal pad must be soldered to the PCB 2. Maximize the PCB area 3. If a multiple layer PCB is used, thermal vias (13 to 25 mil) must be placed underneath the thermal pad to connect to ground plane(s). Do not place thermal reliefs on the vias. Figure 25 shows a typical connection. The thermal resistance for this package is as low as +26°C/W for 2 layer PCB of 0.39" thickness (see Figure 9). The actual junction temperature can be measured at VTJ pin. The thermal performance of the IC is heavily dependent on the layout of the PCB. The user should exercise care during the design phase to ensure the IC will operate within the recommended environmental conditions. FIGURE 25. PCB LAYOUT - 28 Ld HTSSOP PACKAGE Layout Considerations The layout is very important for the converter to function properly. Follow these tips for best performance: 1. Separate the Power Ground ( ) and Signal Ground ( ); connect them only at one point right at the SGND pin 2. Place the input capacitor(s) as close to VIN and PGND pins as possible 3. Make as small as possible the loop from LX pins to L to CO to PGND pins 4. Place R1 and R2 pins as close to the FB pin as possible 5. Maximize the copper area around the PGND pins; do not place thermal relief around them 6. Thermal pad should be soldered to PCB. Place several via holes under the chip to the ground plane to help heat dissipation The demo board is a good example of layout based on this outline. Please refer to the EL7554 Application Brief. GROUND PLANE CONNECTION COMPONENT SIDE CONNECTION |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |