EL7563

FN7296 Rev 2.00

Page 14 of 16

May 13, 2005

Start-up Delay

A capacitor can be added to the EN pin to delay the

converter start-up (Figure 27) by utilizing the pull-up current.

The delay time is approximately:

Thermal Management

The EL7563CM utilizes “fused lead” packaging technology in

conjunction with the system board layout to achieve a lower

thermal resistance than typically found in standard SO20

packages. By fusing (or connecting) multiple external leads

to the die substrate within the package, a very conductive

heat path is created to the outside of the package. This

conductive heat path MUST then be connected to a heat

sinking area on the PCB in order to dissipate heat out and

away from the device. The conductive paths for the SO20

package are the fused leads: # 6, 7, 11, 12, and 13. If a

sufficient amount of PCB metal area is connected to the

fused package leads, a junction-to-ambient resistance of

43°C/W can be achieved (compared to 85°C/W for a

standard SO20 package). The general relationship between

PCB heat-sinking metal area and the thermal resistance for

this package is shown in the Performance Curves section of

this data sheet. It can be readily seen that the thermal

resistance for this package approaches an asymptotic value

of approximately 43°C/W without any airflow, and 33°C/W

with 100 LFPM airflow. Additional information can be found

in Application Note #8 (Measuring the Thermal Resistance

of Power Surface-Mount Packages). For a thermal shutdown

die junction temperature of 135°C, and power dissipation of

1.5W, the ambient temperature can be as high as 70°C

without airflow. With 100 LFPM airflow, the ambient

temperature can be extended to 85°C.

The EL7563CRE utilizes the 28-pin HTSSOP package. The

majority of heat is dissipated through the heat pad exposed

at the bottom of the package. Therefore, the heat pad needs

to be soldered to the PCB. The thermal resistance for this

package is as low as 29°C/W, better than that of the SO20.

Typical performance is shown in the curve section. The

actual junction temperature can be measured at VTJ pin.

Since the thermal performance of the IC is heavily

dependent on the board layout, the system designer should

exercise care during the design phase to ensure that the IC

will operate under the worst-case environmental conditions.

Layout Considerations

The layout is very important for the converter to function

properly. Power Ground (

) and Signal Ground (

)

should be separated to ensure that the high pulse current in

the Power Ground never interferes with the sensitive signals

connected to Signal Ground. They should only be connected

at one point (normally at the negative side of either the input

or output capacitor.)

The trace connected to the FB pin is the most sensitive

trace. It needs to be as short as possible and in a “quiet”

place, preferably between PGND or SGND traces.

needs to be as close to the pin as possible.

The heat of the chip is mainly dissipated through the PGND

pins and through the heat pad at the bottom of the CRE

package. Maximizing the copper area around these pins is

preferable. In addition, a solid ground plane is always helpful

for the EMI performance.

The demo board is a good example of layout based on these

principles. Please refer to the EL7563 Application Brief for

the layout.



1200 C

F





=

FIGURE 27. START-UP DELAY

1

2

15

14

13

12

6

7

8

11

10

9

20

19

EL7563

-

+

STP

STN

C

TIME