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CMV300 Datasheet(PDF) 49 Page - ams AG |
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CMV300 Datasheet(HTML) 49 Page - ams AG |
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49 / 56 page  Reference:CMV300-datasheet-v2.10 CMV300 Datasheet Page 48 of 55 © 2016 CMOSIS bvba Pin number Pin name Description Block Type F7 CLK_IN Master clock input (max 25MHz), 3.3V signaling Sequencer IO F8 SPI_CLK SPI input, 3.3V signaling SPI IO G1 Vtf_L Decouple with with 100nF to GND Pixel array Bias G2 Vtf_L2 Decouple with with 100nF to GND Pixel array Bias G3 VDD20 Connect to 2.2V supply LVDS, ADC Supply G4 VDD33 Connect to 3.3V supply I/O, SPI, ADC Supply G5 Output1_N Image data output LVDS Output G6 Output2_N Image data output LVDS Output G7 Output_ctrl_P LVDS control output LVDS Output G8 T_EXP1 Digital input, 3.3V signaling Sequencer IO H1 Vtf_L3 Decouple with with 100nF to GND Pixel array Bias H2 GND Connect to GND GND H3 GND Connect to GND GND H4 VDDpix Connect to 3.0V supply Pixel array Supply H5 GND Connect to GND GND H6 Output1_P Image data output LVDS Output H7 Output2_P Image data output LVDS Output H8 SYS_RES_N Digital input, 3.3V signaling Sequencer IO 9.2 PARALLEL CMOS OUTPUT MODE PIN LIST The pin list of the CMV300 in parallel CMOS output mode can be found below. Pin number Pin name Description Block Type A1 Test1 No need to connect Sequencer Test pin A2 GND Connect to GND GND A3 GND Connect to GND GND A4 VDDpix Connect to 3.0V supply Pixel array Supply A5 GND Connect to GND GND A6 D4 Image data output, VDD20 signaling CMOS Out Output A7 D6 Image data output, VDD20 signaling CMOS Out Output A8 SPI_OUT SPI output, 3.3V signaling SPI IO B1 Test2 No need to connect Sequencer Test pin B2 Enable_LVDS Connect to GND Sequencer GND B3 VDD20 Connect to 2.2V supply LVDS, ADC Supply B4 VDD33 Connect to 3.3V supply I/O, SPI, ADC Supply B5 D5 Image data output, VDD20 signaling CMOS Out Output B6 D7 Image data output, VDD20 signaling CMOS Out Output B7 D8 Image data output, VDD20 signaling CMOS Out Output B8 SPI_IN SPI input, 3.3V signaling SPI IO C1 VDD33 Connect to 3.3V supply I/O, SPI, ADC Supply C2 VDDpix Connect to 3.0V supply Pixel array Supply C3 R_adc2 Optional, no need to connect ADC Bias C4 R_adc1 Optional, no need to connect ADC Bias C5 D9 Image data output, VDD20 signaling LVDS Output C6 CLK_OUT CMOS output, 3.3V signaling Sequencer Output C7 SPI_EN SPI input, 3.3V signaling SPI IO C8 GND Connect to GND GND D1 Vref Decouple with 100nF to GND ADC Bias D2 Vramp1 Decouple with 100nF to GND ADC Bias D3 Vramp2 Decouple with 100nF to GND ADC Bias D4 NC Not connected NA D5 NC Not connected NA D6 NC Not connected NA D7 LVDS_CLK_N LVDS input clock (N), optional LVDS Input |
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