HIP6301VCBZ datasheet(14/20 Pages) RENESAS

14 / 20 page

HIP6301V, HIP6302V

FN9034 Rev 3.00

Page 14 of 20

May 5, 2008

Droop, Selection of RIN

The average of the currents detected through the RISEN

resistors is also steered to the FB pin. There is no DC return

path connected to the FB pin except for RIN, so the average

current creates a voltage drop across RIN. This drop

increases the apparent VCORE voltage with increasing load

current, causing the system to decrease VCORE to maintain

balance at the FB pin. This is the desired “droop” voltage

used to maintain VCORE within limits under transient

conditions.

With a high dv/dt load transient, typical of high performance

microprocessors, the largest deviations in output voltage

occur at the leading and trailing edges of the load transient.

In order to fully utilize the output-voltage tolerance range, the

output voltage is positioned in the upper half of the range

when the output is unloaded and in the lower half of the

range when the controller is under full load. This droop

compensation allows larger transient voltage deviations and

thus reduces the size and cost of the output filter

components.

RIN should be selected to give the desired “droop” voltage at

the normal full load current 50µA applied through the RISEN

resistor (or at a different full load current if adjusted as in

“Overcurrent, Selecting RISEN” on page 13).

For a Vdroop of 80mV, RIN = 1.6k

The AC feedback components, RFB and Cc, are scaled in

relation to RIN.

Current Balancing

The detected currents are also used to balance the phase

currents.

Each phase’s current is compared to the average of all

phase currents, and the difference is used to create an offset

in that phase’s PWM comparator. The offset is in a direction

to reduce the imbalance.

The balancing circuit can not make up for a difference in

rDS(ON) between synchronous rectifiers. If a FET has a

higher rDS(ON), the current through that phase will be

reduced.

Figures 10 and 11 show the inductor current of a 2-phase

system without and with current balancing.

Inductor Current

The inductor current in each phase of a multiphase buck

converter has two components. There is a current equal to

the load current divided by the number of phases (ILT/n), and

a sawtooth current, (IP-P) resulting from switching. The

sawtooth component is dependent on the size of the

inductors, the switching frequency of each phase, and the

values of the input and output voltage. Ignoring secondary

effects, such as series resistance, the peak-to-peak value of

the sawtooth current can be described by Equation 4.

Where: VCORE = DC value of the output or VID voltage

VIN = DC value of the input or supply voltage

L = value of the inductor

FSW = switching frequency

Example: For VCORE = 1.6V,

VIN = 12V,

L= 1.3µH,

FSW = 250kHz,

Then IP-P = 4.3A

The inductor, or load current, flows alternately from VIN

through Q1 and from ground through Q2. The controller

samples the on-state voltage drop across each Q2 transistor

to indicate the inductor current in that phase. The voltage

drop is sampled 1/3 of a switching period, 1/FSW, after Q1 is

RIN Vdroop

A





(EQ. 3)

IPP

–

VIN VCORE

 V

CORE

–

 F

 V



-----------------------------------------------------------------

(EQ. 4)

FIGURE 10. TWO CHANNEL MULTIPHASE SYSTEM

WITH CURRENT BALANCING DISABLED

FIGURE 11. TWO CHANNEL MULTIPHASE SYSTEM

WITH CURRENT BALANCING ENABLED

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