HIP6303

FN4767 Rev.0.00

Page 8 of 16

December 1999

summing Correction circuit to the Comparator, reduces the

output pulse width of the Comparator to compensate for the

detected “above average” current in that channel.

Droop Compensation

In addition to control of each power channel’s output current,

the average channel current is also used to provide CORE

voltage “droop” compensation. Average full channel current is

defined as 50

amount of voltage droop required at full load current can be

programmed. The average current driven into the FB pin

direction to make the Error Amplifier “see” a higher voltage at

the inverting input, resulting in the Error Amplifier adjusting the

equal to the “droop” voltage. See the “Current Sensing and

Balancing” section for more details.

Applications and Converter Start-Up

Each PWM power channel’s current is regulated. This enables

the PWM channels to accurately share the load current for

enhanced reliability. The HIP6601, HIP6602 or HIP6603

MOSFET driver interfaces with the HIP6303. For more

information, see the HIP6601, HIP6602 or HIP6603 data

sheets.

The HIP6303 is capable of controlling up to 4 PWM power

automatically sets the number of channels. The phase

PWM channels. For example, for three channel operation, the

PWM output signals for a four channel system.

Power supply ripple frequency is determined by the channel

For example, if the channel frequency is set to 250kHz and

there are three channels, the ripple frequency is 750kHz.

The IC monitors and precisely regulates the CORE voltage of a

microprocessor. After initial start-up, the controller also

provides protection for the load and the power supply. The

following section discusses these features.

Initialization

The HIP6303 usually operates from an ATX power supply.

Many functions are initiated by the rising supply voltage to the

Start and other functions are initialized during this interval.

These circuits are controlled by POR, Power-On Reset. During

this interval, the PWM outputs are driven to a three state

condition that makes these outputs essentially open. This state

results in no gate drive to the output MOSFETS.

level to insure proper internal function, the PWM outputs are

enabled and the Soft-Start sequence is initiated. If for any

POR circuit shuts the converter down and again three states

the PWM outputs.

Soft-Start

4.375V, the Soft-Start sequence is initiated. Soft-Start, by its

slow rise in CORE voltage from zero, avoids an over-current

condition by slowly charging the discharged output capacitors.

This voltage rise is initiated by an internal DAC that slowly

raises the reference voltage to the error amplifier input. The

voltage rise is controlled by the oscillator frequency and the

DAC within the HIP6303. Therefore, the output voltage is

effectively regulated as it rises to the final programmed CORE

voltage value.

For the first 32 PWM switching cycles, the DAC output remains

inhibited and the PWM outputs remain three stated. From the

33rd cycle and for another, approximately 150 cycles the PWM

output remains low, clamping the lower output MOSFETs to

ground, see Figure 3. The time variability is due to the Error

Amplifier, Sawtooth Generator and Comparators moving into

their active regions. After this short interval, the PWM outputs

are enabled and increment the PWM pulse width from zero

duty cycle to operational pulse width, thus allowing the output

voltage to slowly reach the CORE voltage. The CORE voltage

will reach its programmed value before the 2048 cycles, but

the PGOOD output will not be initiated until the 2048th PWM

switching cycle.

160

s, the PWM outputs are held in a three state level as

explained above. After this period and a short interval

PWM 1

PWM 2

PWM 3

PWM 4

FIGURE 2. FOUR PHASE PWM OUTPUT AT 500kHz