| Electronic Components Datasheet Search |
|
ISL6540ACRZ Datasheet(PDF) 21 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
ISL6540ACRZ Datasheet(HTML) 21 Page - Renesas Technology Corp |
|
21 / 22 page ![]() FN6288 Rev 5.00 Page 21 of 22 Oct 7, 2008 ISL6540A Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2006-2008. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. the largest component of power dissipation for both the upper and the lower MOSFETs. These losses are distributed between the two MOSFETs according to duty factor (see the equations below). The upper MOSFET exhibits turn-on and turn-off switching losses as well as the reverse recover loss, while the synchronous rectifier exhibits body-diode conduction losses during the leading and trailing edge dead times. where D is the duty cycle = VO/VIN; Qrr is the reverse recover charge; tDLand tDT are leading and trailing edge dead time, and tON and tOFF are the switching intervals. These equations do not include the gate-charge losses that are proportional to the total gate charge and the switching frequency and partially dissipated by the internal gate resistance of the MOSFETs. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. PLOWER IO 2 I 2 12 -------- + rDS ON ,L NL --------------------------- 1D – P DEAD + = PDEAD IO I 12 ------ + V DT tDT IO I 12 ------ – V DL tDL + FS = PSW IO I 12 ------ + t OFF IO I 12 ------ – t ON + VIN F S = PUPPER IO 2 I 2 12 -------- + rDS ON ,U NU ---------------------------- DPSW PQrr ++ = PQrr Qrr VIN F S = (EQ. 22) |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |