VG509A

- 2 -

Ver 1.2

5. Pin Function Description

Pi n Na m e

I/ O

Fu nc ti o n D e sc ri p t i o n

PB 0 , PB 1, P B 3 ~ PB 5

I/ O

Po r t B , TT L i n p u t l e v e l

RT CC/P B 2

I / O

Re al Time Cl ock / Co u n t er, S c h m itt T r ig g er i n p u t le v e l s

/MC L R

I

Mas t e r Clear, Sc hmitt T r ig g er i n put le v e l s

OSC 1

I

Os c i ll a t o r I n p u t

OSC 2

O

Os c i ll a t o r Ou t p u t

Vd d

P o w e r s u p p l y

V ss

Gr o u n d

6. Memory Map

(A ) R e gi s t e r M a p

Ad dr ess

De scri pt io n

BA NK 0

00

I n direct A d dr e s s i ng Re g i s t er

01

RT CC

02

P C

03

S T A T U S

04

MS R

06

P o rt B

07 ~1F

G e ne ra l pur p ose re gi st ers

BA NK 1

30 ~3F

G e ne ra l pur p ose re gi st ers

( 1 )I A R ( I n di r e c t A d d r e ss Reg i s t er) : R0

( 2 ) RT CC (R ea l T i me C ount er / C o u n t er Re gi s t e r) : R1

(3 ) PC (P ro g r a m C o u n t er ) : R2

Wr it e P C , C A LL - -- a l w a ys 0

J U MP -- - f r o m in st r u ct i on wor d

RTI W , RET - -- f r o m S T AC K

Write PC, JUMP, CA LL --- f r o m STATU S b5

RTI W , RET - -- f r o m S T AC K

Wr it e P C --- f r o m AL U

JU M P , CA L L - - - f r o m ins tru c ti o n w o r d

R T IW , R E T -- - f r o m STA C K

A9

A8

A7~ A0