XRT83SL38IB datasheet(71/89 Pages) EXAR

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XRT83SL38

OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

PRELIMINARY

REV. P1.1.0

TABLE 36: MICROPROCESSOR REGISTER #129, BIT DESCRIPTION

10000001

NAME

FUNCTION

TYPE

RESET

VALUE

BIT #

Reserved

R/W

CLKSEL2

Clock Select Inputs for Master Clock Synthesizer bit 2:

In Host mode, CLKSEL[2:0] are input signals to a programma-

ble frequency synthesizer that can be used to generate a mas-

ter clock from an external accurate clock source according to

the following table;

In Hardware mode, the state of these signals are ignored and

the master frequency PLL is controlled by the corresponding

Hardware pins.

R/W

CLKSEL1

Clock Select inputs for Master Clock Synthesizer bit 1:

See description of bit D6 for function of this bit.

R/W

CLKSEL0

Clock Select inputs for Master Clock Synthesizer bit 0:

See description of bit D6 for function of this bit.

R/W

MCLKRATE

Master clock Rate Select: The state of this bit programs the

Master Clock Synthesizer to generate the T1/J1 or E1 clock.

The Master Clock Synthesizer will generate the E1 clock when

MCLKRATE = “0”, and the T1/J1 clock when MCLKRATE =

“1”.

R/W

RXMUTE

Receive Output Mute: Writing a “1” to this bit, mutes receive

outputs at RPOS/RDATA and RNEG/LCV pins to a “0” state for

any channel that detects an RLOS condition.

NOTE: RCLK is not muted.

R/W

2048

1544

MCLKE1

kH z

128

256

128

2048

1544

MCLKT 1

kHz

1544

2048

1544

2048

CL KOUT/

kH z

1544

2048

1544

2048

1544

2048

1544

2048

1544

2048

1544

2048

1544

CLK SEL 0

CL KSEL 1

CL KSEL 2

1544

2048

1544

MCLKR AT E

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