ISL8104

FN9257 Rev 2.00

Page 10 of 14

March 7, 2008

regulator. Change the numerical factor (0.7) below to

lower in frequency helps reduce the gain of the

compensation network at high frequency, in turn reducing

the HF ripple component at the COMP pin and minimizing

resultant duty cycle jitter.

It is recommended that a mathematical model be used to

plot the loop response. Check the loop gain against the error

amplifier’s open-loop gain. Verify phase margin results and

adjust as necessary. Equation 13 describes the frequency

COMPENSATION BREAK FREQUENCY EQUATIONS

Figure 8 shows an asymptotic plot of the DC/DC converter’s

gain vs frequency. The actual Modulator Gain has a high gain

peak dependent on the quality factor (Q) of the output filter,

which is not shown. Using the previously mentioned guidelines

should yield a compensation gain similar to the curve plotted.

The open loop error amplifier gain bounds the compensation

constructed on the log-log graph of Figure 8 by adding the

multiplying the modulator transfer function and the

compensation transfer function and then plotting the

resulting gain.

A stable control loop has a gain crossing with close to a

-20dB/decade slope and a phase margin greater than 45°.

Include worst case component variations when determining

phase margin. The mathematical model presented makes a

number of approximations and is generally not accurate at

frequencies approaching or exceeding half the switching

frequency. When designing compensation networks, select

target crossover frequencies in the range of 10% to 30% of

Component Selection Guidelines

Output Capacitor Selection

An output capacitor is required to filter the output and supply

the load transient current. The filtering requirements are a

function of the switching frequency and the ripple current.

The load transient requirements are a function of the slew

rate (di/dt) and the magnitude of the transient load current.

These requirements are generally met with a mix of

capacitors and careful layout.

For applications that have transient load rates above 1A/ns,

high frequency capacitors initially supply the transient and

slow the current load rate seen by the bulk capacitors. The

bulk filter capacitor values are generally determined by the

ESR (effective series resistance) and voltage rating

requirements rather than actual capacitance requirements.

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

specific decoupling requirements.

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors.

The bulk capacitor’s ESR will determine the output ripple

voltage and the initial voltage drop after a high slew-rate

transient. An aluminum electrolytic capacitor's ESR value is

related to the case size with lower ESR available in larger

case sizes. However, the equivalent series inductance

(ESL) of these capacitors increases with case size and can

reduce the usefulness of the capacitor to high slew-rate

----------- 1

–

--------------------

=

1

2

 R





-----------------------------------------------

=

(EQ. 12)



-------------------------------

1s f

 ESR C



+

1s f

 ESR DCR

+

 C



s



++

-----------------------------------------------------------------------------------------------------------



=

1s f

 R



+

sf

 R

1

+





----------------------------------------------------



=

1s f

 R

1

+

 C

3



+

1s f

 R



+

 1s f

 R

2



+

---------------------









+









-------------------------------------------------------------------------------------------------------------------------



=

where s f





2

 fj



=

(EQ. 13)

1

2

 R



-------------------------------

=

1

2

 R

1

+

 C

3



-------------------------------------------------

=

1

2

 R

2



+

---------------------



---------------------------------------------

=

1

2

 R



-------------------------------

=

(EQ. 14)

0

OPEN LOOP E/A GAIN

COMPENSATION GAIN

FREQUENCY

MODULATOR GAIN

FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

CLOSED LOOP GAIN

20

R2

R1

--------





log

LOG

20



IN

VOSC

----------------------------------

log