ISL8501IRZ datasheet(13/19 Pages) RENESAS

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ISL8501

FN6500 Rev 1.00

Page 13 of 19

July 12, 2007

Detailed Description

The ISL8501 combines a standard buck PWM controller with

an integrated switching MOSFET and two low dropout (LDO)

linear regulators with internal pass devices. The buck

controller drives an internal N-Channel MOSFET and

requires an external diode to deliver load current up to 1A.

A Schottky diode is recommended for improved efficiency

and performance over a standard diode. The standard buck

regulator can operate from either an unregulated DC source,

such as a battery, with a voltage ranging from +6.0V to +25V,

or from a regulated system rail of +5V. When operating from

+6V or greater, the controller is biased from an internal +5V

LDO voltage regulator. The converter output is regulated

down to 0.6V from either input source. Each LDO linear

regulator can source up to 500mA continuous output current

with +2V or greater input supply and +1.0V or higher output

voltage. These features make the ISL8501 ideally suited for

FPGA and wireless chipset power applications.

The PWM control loop uses a single output voltage loop with

input voltage feed forward which simplifies feedback loop

compensation and rejects input voltage variation. External

feedback loop compensation allows flexibility in output filter

component selection. The regulator switches at a fixed

500kHz.

The buck regulator and LDOs are provided with independent

current limits. The current limit in the buck regulator is

achieved by monitoring the drain-to-source voltage drop of

the internal switching power MOSFET. The current limit

threshold is internally set at 2A. The part also features

undervoltage protection by latching the switching MOSFET

driver to the OFF state during an overcurrent, when the

output voltage is lower than 70% of the regulated output.

This helps minimize power dissipation during a short-circuit

condition. Due to only the switching power MOSFET

integration, there is no overvoltage protection feature for this

part.

The ISL8501 monitors and controls the pass transistor’s

gate voltage to limit the output current. The current limits for

both LDOs is 800mA typical. Neither LDO has overvoltage or

undervoltage protection. When the current limit in either

output is reached, the output no longer regulates the voltage,

but regulates the current to the value of the current limit.

+5V Internal Bias Supply (VCC)

Voltage applied to the VIN pin with respect to GND is

regulated to +5V DC by an internal LDO regulator. The

output of the LDO, VCC, is the bias voltage used by all the

internal control and protection circuitry. The VCC pin

requires a ceramic capacitor connected to GND. The

capacitor serves to stabilize the LDO and to decouple load

transients.

The input voltage range for the ISL8501 is specified as +6V

to +25V or +5V ±10%. In the case of an unregulated supply

case, the power supply is connected to VIN only. Once

enabled, the linear regulator will turn-on and rise to +5V on

VCC. In the +5V supply case, the VCC and VIN pins must be

tied together to bypass the LDO. The external decoupling

capacitor is still required in this mode. Do not short VCC to

GND.

Operation Initialization

The power-on reset circuitry and enable inputs prevent false

startup of the PWM regulator and LDO outputs. Once all the

input criteria are met, the controller soft-starts the output

voltage to the programmed level.

Power-On Reset and Undervoltage Lockout

The PWM portion of the ISL8501 automatically initializes

upon receipt of input power. The power-on reset (POR)

function continually monitors the VCC and PVCC voltages.

While both are below their POR thresholds, the controller

inhibits switching of the internal power MOSFET. Once

exceeded, the controller initializes the internal soft-start

circuitry. If either input supply drops below their falling POR

threshold during soft-start or operation, the buck regulator

latches off.

Independent LDO supply inputs (VIN_LDO1 and VIN_LDO2)

allow flexibility in partitioning linear regulator power. Power

supplies connected to either LDO supply input must exceed

the undervoltage lockout (UVLO) threshold before that LDO

is initialized. If the input supply drops below the falling UVLO

threshold during operation, the low dropout voltage regulator

latches off.

Enable and Disable

All internal power devices are held in a high-impedance

state, which ensures they remain off while in shutdown

mode. Typically the enable input for a specific output is

toggled high after the input supply to that regulator is active

and the internal LDO has exceeded its POR threshold.

The EN pin enables the buck controller portion of the

ISL8501. When the voltage on the EN pin exceeds the POR

rising threshold, the controller initiates the soft-start function

for the PWM regulator. If the voltage on the EN pin drops

below the POR falling threshold, the buck regulator shuts

down.

Individual LDO enable inputs (EN_LDO1 and EN_LDO2)

allow independent control of each regulator. Make sure EN

is on, when the voltage on either pin exceeds the POR rising

threshold, linear regulator operation is initiated for that

controller. If the voltage then drops below the hysteresis

level for the enable pin, the LDO shuts down.

Pulling the EN low simultaneously puts all outputs into

shutdown mode, and supply current drops to 10

A typical.

Soft-Start

Once the input supply latch and enable threshold are met,

the soft-start function is initialized. The soft-start circuitry

begins sourcing 30

A, from an internal current source, which

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