Data Sheet

ADMV7710

Rev. 0 | Page 13 of 17

THEORY OF OPERATION

The circuit architecture of the ADMV7710 power amplifier is

shown in Figure 45. The ADMV7710 uses four cascaded gain

stages to form an amplifier with a combined gain of 24 dB and a

last stage, a coupler taps off a small portion of the output signal.

The coupled signal is presented to an on-chip diode detector for

external monitoring of the output power. A matched reference

diode is included to correct detector temperature dependencies.

See the application circuit shown in Figure 46 for further details

on biasing the different blocks and using the detector features.

RFIN

RFOUT

VDET VREF

Figure 45. Power Amplifier Circuit Architecture