ISL6530CBZ datasheet(14/18 Pages) RENESAS

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ISL6530

FN9052 Rev 2.00

Page 14 of 18

Nov 15, 2004

Ensure that both MOSFETs are within their maximum junction

temperature at high ambient temperature by calculating the

temperature rise according to package thermal-resistance

specifications. A separate heatsink may be necessary

depending upon MOSFET power, package type, ambient

temperature and air flow.

Given the reduced available gate bias voltage (5V), logic-

level or sub-logic-level transistors should be used for both N-

MOSFETs. Caution should be exercised when using devices

with very low gate thresholds (VTH). The shoot-through

protection circuitry may be circumvented by these

MOSFETs. Very high dv/dt transitions on the phase node

may cause the Miller capacitance to couple the lower gate

with the phase node and cause an undesireable turn on of

the lower MOSFET while the upper MOSFET is on.

Bootstrap Component Selection

External bootstrap components, a diode and capacitor, are

required to provide sufficient gate enhancement to the upper

MOSFET. The internal MOSFET gate driver is supplied by

the external bootstrap circuitry as shown in Figure 10. The

boot capacitor, CBOOT, develops a floating supply voltage

referenced to the PHASE pin. This supply is refreshed each

cycle, when DBOOT conducts, to a voltage of VCC less the

boot diode drop, VD, plus the voltage rise across QLOWER.

Just after the PWM switching cycle begins and the charge

transfer from the bootstrap capacitor to the gate capacitance

is complete, the voltage on the bootstrap capacitor is at its

lowest point during the switching cycle. The charge lost on

the bootstrap capacitor will be equal to the charge

transferred to the equivalent gate-source capacitance of the

upper MOSFET as shown:

where QGATE is the maximum total gate charge of the upper

MOSFET, CBOOT is the bootstrap capacitance, VBOOT1 is

the bootstrap voltage immediately before turn-on, and

VBOOT2 is the bootstrap voltage immediately after turn-on.

The bootstrap capacitor begins its refresh cycle when the

gate drive begins to turn-off the upper MOSFET. A refresh

cycle ends when the upper MOSFET is turned on again,

which varies depending on the switching frequency and

duty cycle.

The minimum bootstrap capacitance can be calculated by

rearranging the previous equation and solving for CBOOT.

Typical gate charge values for MOSFETs considered in

these types of applications range from 20 to 100nC. Since

the voltage drop across QLOWER is negligible, VBOOT1 is

simply VCC - VD. A Schottky diode is recommended to

minimize the voltage drop across the bootstrap capacitor

during the on-time of the upper MOSFET. Initial calculations

with VBOOT2 no less than 4V will quickly help narrow the

bootstrap capacitor range.

For example, consider an upper MOSFET is chosen with a

maximum gate charge, Qg, of 100nC. Limiting the voltage

drop across the bootstrap capacitor to 1V results in a value

of no less than 0.1

F. The tolerance of the ceramic capacitor

should also be considered when selecting the final bootstrap

capacitance value.

A fast recovery diode is recommended when selecting a

bootstrap diode to reduce the impact of reverse recovery

charge loss. Otherwise, the recovery charge, QRR, would

have to be added to the gate charge of the MOSFET and

taken into consideration when calculating the minimum

bootstrap capacitance.

ISL6530

GND

LGATEn

UGATEn

PHASEn

BOOTn

VIN

NOTE:

VG-S ª VCC

CBOOT

DBOOT

QUPPER

QLOWER

FIGURE 10. UPPER GATE DRIVE BOOTSTRAP

VG-S ª VCC -VD

VCC

QGATE

CBOOT VBOOT1 VBOOT2

–





CBOOT

QGATE

VBOOT1 V

–

BOOT2

-----------------------------------------------------



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