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ISL5585ECM Datasheet(PDF) 21 Page - Renesas Technology Corp |
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ISL5585ECM Datasheet(HTML) 21 Page - Renesas Technology Corp |
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21 / 23 page ![]() ISL5585 FN6026 Rev 6.00 Page 21 of 23 October 21, 2004 Special Considerations for the QFN Package The new Quad Flatpack No-lead (QFN) package offers a significant footprint reduction (65%) and improved thermal performance with respect to the 28 lead PLCC. To realize the thermal enhancements and maintain the high voltage (-100V) performance, the exposed pad on the bottom of the QFN package should be soldered to a power/heat sink plane that is electrically connected to the ISL5585 Substrate Common Connection (SCC) pin. The heat is distributed evenly across the board by way of the heat sink plane. This is accomplished by using conductive thermal vias. Reference technical brief TB379 and AN9922 for additional information on thermal characterization and board layout considerations. TABLE 2. ISL5585 3V APPLICATION CIRCUIT COMPONENTS COMPONENT VALUE TOL RATING U1 - Ringing SLIC ISL5585 N/A N/A RTL 18.7k 1% 0.1W RRT 23.7k 1% 0.1W RSH 49.9k 1% 0.1W RIL 71.5k 1% 0.1W RS 66.5k 1% 0.1W RF 30.1k 1% 0.1W RA 36.5k 1% 0.1W RB 42.2Kk 1% 0.1W RIN 45.3k 1% 0.1W CRS, CTX, CRT, CPOL 0.47 F 20% 10V CDC, CFB 4.7 F 20% 6.3V CPS1 0.1 F 20% >100V CPS2, CPS3 0.1 F 20% 100V D1 1N400X type with breakdown > 100V. RP1, RP2 Standard applications will use 49 per side. Protection resistor values are application dependent and will be determined by protection requirements. Design Parameters: Ring Trip Threshold = 76mAPEAK, Switch Hook Threshold = 12mA, Loop Current Limit = 24.6mA, Synthesize Device Impedance = (3*66.5k /400 = 498.8, with 49.9 protection resistors, impedance across Tip and Ring terminals = 599 . Transient current limit = 95mA. FIGURE 17. ISL5585 3.3V APPLICATION CIRCUIT AUX VRS TIP VFB BGND AGND RING VTX -IN SH RT CDC ILIM ISL5585 VCC POL CRS RIL CFB RS RSH CRT RRT CPOL CDC U1 RP1 RP2 VCC VBL VBH D1 1N4004 CPS1 CPS3 CPS2 TL RTL + - RF RA RB CODEC +2.4V TX IN RIN V2W + - PCM to V2W Gain = +3.33dB, digital gain set to 0dB V2W to PCM Gain = -9.3 dB, digital gain set to 0dB Digital Gain 0dB Digital Gain 0dB PCM PCM 0 dBm0, CODEC output voltage = 0.531Vrms 0 dBm0, V2W = 0.7795Vrms Design Equations RS = 133.33(ZL - 2RP) Gain PCM to V2W = RS/RIN = 66.5k/45.3k =1.46 66.5k 45.3k V2W to PCM Gain = V2W (G2-4)(RF/RA) = (0.7795)(0.416)(30.1k/36.5k) = 0.267 30.1k 36.5k 42.2k 0.47uF 0.47uF 0.47uF dB Gain =20log (0.7795/ 0.531) = +3.33dB dB Gain =20log (0.267/0.7795) = - 9.3dB 600 49.9 49.9 |
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