Electronic Components Datasheet Search
  English  ▼

X  

ISL54500 Datasheet(PDF) 13 Page - Renesas Technology Corp

Part # ISL54500
Description  1.8V to 5.5V, 5W, Single SPDT Analog Switch
PDF  13 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ISL54500 Datasheet(HTML) 13 Page - Renesas Technology Corp

Back Button ISL54500 Datasheet HTML 5Page - Renesas Technology Corp ISL54500 Datasheet HTML 6Page - Renesas Technology Corp ISL54500 Datasheet HTML 7Page - Renesas Technology Corp ISL54500 Datasheet HTML 8Page - Renesas Technology Corp ISL54500 Datasheet HTML 9Page - Renesas Technology Corp ISL54500 Datasheet HTML 10Page - Renesas Technology Corp ISL54500 Datasheet HTML 11Page - Renesas Technology Corp ISL54500 Datasheet HTML 12Page - Renesas Technology Corp ISL54500 Datasheet HTML 13Page - Renesas Technology Corp  
Zoom Inzoom in Zoom Outzoom out
 13 / 13 page
background image
ISL54500
FN6549 Rev 2.00
Page 13 of 13
November 9, 2009
Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)
B
D
A
E
0.10C
2X
PIN 1
TOP VIEW
0.10C
2X
REFERENCE
DETAIL A
0.10C
0.08C
7X
A3
A1
A
C
SEATING
PLANE
5X
L
e
1
3
64
4X
BOTTOM VIEW
SIDE VIEW
0.10 CA B
0.05C
b6X
NOTE 3
L1
DETAIL A
DETAIL B PIN 1 LEAD
0.1x45°
CHAMFER
DETAIL B
A3
A1
1.40
LAND PATTERN
1.00
0.30
0.35
0.20
0.45
0.40
0.20
10
L6.1.2x1.0A
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL
MILLIMETERS
NOTES
MIN
NOMI-
NAL
MAX
A
0.45
0.50
0.55
-
A1
-
-
0.05
-
A3
0.127 REF
-
b
0.15
0.20
0.25
5
D
0.95
1.00
1.05
-
E
1.15
1.20
1.25
-
e
0.40 BSC
-
L
0.30
0.35
0.40
-
L1
0.40
0.45
0.50
-
N
6
2
Ne
3
3
0-
12
4
Rev. 2 8/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-
1994.
2. N is the number of terminals.
3. Ne refers to the number of terminals on E side.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is
measured between 0.15mm and 0.30mm from the
terminal tip.
6. The configuration of the pin #1 identifier is optional, but
must be located within the zone indicated. The pin #1
identifier may be either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land
Pattern Design effort, see Intersil Technical Brief TB389.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com