TLE7189F

Data Sheet

24

Rev. 2.2, 2016-01-28

5.3.20

Slew rate

I

SC

–

10

–

V/µs

Gain>= 5;

R

C

5.3.21

Large signal open loop voltage gain

(DC)

A

OL

80

100

–

dB

–

5.3.22

Unity gain bandwidth

GBW

10

20

–

MHz

R

C

5.3.23

Phase margin1)

Φ

M

–

50

–

°

Gain>= 5;

R

C

5.3.24

Gain margin1)

A

M

–12

–

db

R

C

5.3.25

Bandwidth

BW

G

1.6

–

–

MHz

Gain=15;

R

C

R

5.3.26

Output settle time to 98%

t

set

–

1

1.8

µs

Gain=15;

R

C

0.2<

V

R

5.3.27

Output rise time 10% to 90%

t

Irise

–

–1µs

5.3.28

Output fall time 90% to 10%

t

Ifall

–

–1µs

1) Not subject to production test; specified by design

2) Without considering any offsets such as input offset voltage, internal miss match and assuming no tolerance error in

external resistors.

Electrical Characteristics - Current sense signal conditioning (cont’d)

V

flowing into pin (unless otherwise specified)

Pos.

Parameter

Symbol

Limit Values

Unit

Conditions

Min.

Typ.

Max.