SLGSSTU32864 datasheet(7/11 Pages) ETC

7 / 11 page

Silego Technology Inc.

(408) 327-8800

SLGSSTU32864E

PRELIMINARY

Data is subject to change.

Mar 5, 2004

SLGSSTU32864 DC Electrical Characteristics

VDD = 1.8 +/-0.1V (unless otherwise stated)

Timing Requirements:

(over operating free-air temperature range, unless otherwise noted)

Input slew rates are 1V/ns + 20%.

Notes: 4. Data and VREF inputs must be held low for a minimum time (tACT max) after RESET driven high

5. Data, VREF, and CLK,CLK inputs must be held at valid logic (high or low) levels for a minimum time

(tINACT max) after RESET driven low

PARAMETER

CONDITIONS

VDD

MIN

TYP

MAX UNITS

VOH

IOH = -100µA

1.7V -1.9V VDD - 0.2

IOH = -6mA

1.7V

1.2

VOL

IOL = 100µA

1.7V -1.9V

0.2

IOL = 6mA

1.7V

0.5

All Inputs

VI = VDD or GND

IO = 0

1.9V

µA

IDD

Standby (Static) RESET = GND

1.9V

100

µA

Operating

(Static)

VI = VIH(AC) or VIL(AC),

RESET = VDD

IDDD

Dynamic

operating

(clock only)

RESET = VDD,

VI = VIH(AC) or VIL(AC),

CLK & CLK switching

50% duty cycle

1.8V

µA/

MHz

Dynamic

Operating 1:1

(each data

input)

RESET = VDD,

VI = VIH(AC) or VIL(AC),

CLK & CLK switching

50% duty cycle. One

data input switching at

half clock frequency,

50%duty cycle

µA/

clock

MHZ/

data

Dynamic

Operating 1:2

(each data

input)

µA/

clock

MHZ/

data

Data Inputs

VI = VREF + 250 mV

1.8V

2.5

3.8

CLK and CLK

VICR=0.9V, VI(PP) = 600mV

4.4

4.8

5.2

RESET

VI = VDD or GND

4.2

4.6

PARAMETER

MIN

MAX

UNITS

fclock Clock frequency

300

MHz

Pulse duration. CLK,CLK high or low

tACT

Differential active time4

tINACT Differential inactive time5

Setup time

DCS before CLK

, CLK , CSR high

0.7

DCS before CLK

, CLK , CSR low

0.5

Hold time

CSR, ODT, CKE, and Data before CLK

, CLK

0.5

DCS, CSR, ODT, CKE, Data before CLK

, CLK

0.5

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