ADRF6520ACPZ-R7 datasheet(25/29 Pages) AD

25 / 29 page

Data Sheet

ADRF6520

Rev. 0 | Page 25 of 29

R/W

A14

A13

A12

A11

A10

DON’T CARE

SDIO

SCLK

DON’T CARE

tDH

tDS

tHI

tCLK

tACCESS

tLO

R/W

A14

A13

A12

A11

A10

DON’T CARE

SDIO

SCLK

DON’T CARE

tDH

tDS

tHI

tCLK

tACCESS

tLO

SETUP AND HOLD TIMEING MEASUREMENTS.

LEVEL MUST BE AT THE SAME HEAD AND TAIL.

Figure 69. SPI Port Read and Write Timing Diagrams

Table 7. SPI Port Timing Specifications

Symbol

Description

tDS

Setup time between data and rising edge of SCLK

tDH

Hold time between data and rising edge of SCLK

tCLK

Period of the clock

Setup time between CS and SCLK

Hold time between CS and SCLK

tHI

Minimum period that SCLK must be in a logic high state

tLO

Minimum period that SCLK must be in a logic low state

Maximum time delay between CS deactivation and

SDIO or SDO bus return to high impedance

tACCESS

Maximum time delay between falling edge of SCLK

and output data valid for a read operation

B24 = 0 initiates a write, and B24 = 1 initiates a read. The

instruction word (B24 followed by the 15 address bits) is written

to the device, MSB first (as shown in Figure 69), followed by the

data. The SDIO pin becomes an output pin after receiving the

instruction header with a readback request. In read mode, the

SDIO line must be changed from an input to an output in the

half cycle of SCLK between the last rising edge of SCLK of the

instruction and the following falling edge. When CS is deasserted,

SDIO returns to high impedance until the next read transaction.

The interface is capable of reading and writing at speeds of at

least 25 MHz (tCLK = 40 ns). The hold time (tDH) is less than 25%

of the clock period. The setup time (tDS) is less than 25% of the

clock period. There is no minimum interface speed.

Write Cycle

The instruction word, followed by the register data, is written

serially into the device through the SDIO pin on the rising

edges of the interface clock, SCLK. The device is configured in

MSB first mode and descending addressing.

Read Cycle

The instruction word is written to the device MSB first,

followed by the data. Chip readback is sent via the SDIO. The

SDIO pin becomes an output pin after receiving the instruction

header with a readback request. In read mode, the SDIO line

must be changed from an input to an output in the half cycle of

SCLK between the last rising edge of SCLK of the instruction

and the following falling edge. When CS is deasserted, SDIO

returns to high impedance until the next read transaction.

ADRF6520ACPZ-R7 Datasheet(PDF) 25 Page - Analog Devices

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