AIC-43C97

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Other Features

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Introduction

The AIC-43C97C is an automated, high-performance, integrated, SCSI protocol controller designed for

SCSI-2/SCSI-3 embedded peripheral applications. The AIC-43C97C provides the necessary support for

interfacing the SCSI bus to a peripheral using a DMA bus. It consists of three main blocks: SCSI Bus In-

terface, Buffer Controller and associated embedded 8 Kbyte FIFO RAM, and DMA Interface. Automation

within this device enables a more efficient SCSI operation, thus minimizing microprocessor involvement.

The AIC-43C97C Ultra-2 SCSI Protocol chip supports the Low Voltage Differential (LVD) feature required

to enable connectivity to the Ultra-2 80 MB/s bus. The AIC-43C97C also maintains backward compatibility

to single-ended operation by detecting signal variance on the SCSI bus and automatically defaulting to the

proper SCSI bus characteristic of single ended or Low Voltage Differential.

An embedded 960 MHz Phase Locked Loop Frequency Synthesizer provides high resolution on selection

of SCLK and BCLK frequencies for the SCSI bus.

The AIC-43C97C supports both Initiator and Target modes. As a Target, the SCSI sequencer handles

SCSI commands with as few as 0 interrupts to the microprocessor. In the case of Auto Matched Read or

Write operation, 0 interrupts may be generated requiring no additional processing time. The sequencer

can be custom programmed to handle most tasks to achieve maximum performance. The AIC-43C97C

also has automated support for SCAM Level 1 and SCAM Level 2.

The AIC-43C97C has incorporated three DMA modes: an ATA mode which runs in Master and Slave

Modes and sustains DMA transfers to 40 MB/s in 16-bit mode, a SCSI mode which runs in asynchronous

and synchronous initiator modes up to 100 MB/s, and a Generic DMA mode that sustains DMA transfers

up to 40 MB/s in 16-bit mode.

Figure 2. AIC-43C97C Block Diagram

Ultra-2 SCSI

Host (SCSI)

Host Interface

DMA

“HIF”

MPU

DMACLK/2

REFCLK

Bus

SLCLK

MPU

Interface

“MPIF”

Buffer

Manager

“BUFMAN”

DMA

Interface

“DIF”

Frequency

Synthesizer

“FSYN”

Buffer

RAM

“BUFRAM”

DMACLK

Bus

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