LM5105SD datasheet(8/12 Pages) NSC

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Timing Diagrams

Operational Notes

The LM5105 is a single PWM input Gate Driver with Enable

that offers a programmable deadtime. The deadtime is set

with a resistor at the RDT pin and can be adjusted from

100ns to 600ns. The wide deadtime programming range

provides the flexibility to optimize drive signal timing for a

wide range of MOSFETS and applications.

The RDT pin is biased at 3V and current limited to 1 mA

maximum programming current. The time delay generator

will accommodate resistor values from 5k to 100k with a

deadtime time that is proportional to the RDT resistance.

Grounding the RDT pin programs the LM5105 to drive both

outputs with minimum deadtime.

STARTUP AND UVLO

Both top and bottom drivers include under-voltage lockout

(UVLO) protection circuitry which monitors the supply volt-

age (V

DD) and bootstrap capacitor voltage (HB – HS) inde-

pendently. The UVLO circuit inhibits each driver until suffi-

cient supply voltage is available to turn-on the external

MOSFETs, and the UVLO hysteresis prevents chattering

during supply voltage transitions. When the supply voltage is

applied to the V

DD pin of LM5105, the top and bottom gates

are held low until V

DD exceeds the UVLO threshold, typically

about 6.9V. Any UVLO condition on the bootstrap capacitor

will disable only the high side output (HO).

20137503

LM5105 Input - Output Waveforms

FIGURE 2.

20137504

LM5105 Switching Time Definitions: t

LPLH,tLPHL,tHPLH,tHPHL

FIGURE 3.

20137530

LM5105 Enable: t

FIGURE 4.

20137531

LM5105 Dead-time: DT

FIGURE 5.

LM5105SD Datasheet(PDF) 8 Page - National Semiconductor (TI)

LM5105SD Datasheet(HTML) 8 Page - National Semiconductor (TI)

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