LTC1743CFW datasheet(12/24 Pages) LINER

12 / 24 page

LTC1743

1743f

APPLICATIO S I FOR ATIO

Aperture Delay Time

The time from when a rising ENC equals the ENC voltage

to the instant that the input signal is held by the sample and

hold circuit.

Aperture Delay Jitter

The variation in the aperture delay time from conversion to

conversion. This random variation will result in noise

when sampling an AC input. The signal to noise ratio due

to the jitter alone will be:

SNRJITTER = –20log (2π) • FIN • TJITTER

CONVERTER OPERATION

As shown in Figure 1, the LTC1743 is a CMOS pipelined

multistep converter. The converter has four pipelined ADC

stages; a sampled analog input will result in a digitized

value five cycles later, see the Timing Diagram section.

The analog input is differential for improved common

mode noise immunity and to maximize the input range.

Additionally, the differential input drive will reduce even

order harmonics of the sample-and-hold circuit. The en-

code input is also differential for improved common mode

noise immunity.

The LTC1743 has two phases of operation, determined by

the state of the differential ENC/ENC input pins. For brev-

ity, the text will refer to ENC greater than ENC as ENC high

and ENC less than ENC as ENC low.

Each pipelined stage shown in Figure 1 contains an ADC,

a reconstruction DAC and an interstage residue amplifier.

In operation, the ADC quantizes the input to the stage and

the quantized value is subtracted from the input by the

DAC to produce a residue. The residue is amplified and

output by the residue amplifier. Successive stages operate

out of phase so that when the odd stages are outputting

their residue, the even stages are acquiring that residue

and visa versa.

INTERNAL

CLOCK SIGNALS

INTERNAL

REFERENCES TO ADC

DIFFERENTIAL

INPUT

LOW JITTER

CLOCK

DRIVER

RANGE

SELECT

2.5V

REFERENCE

ENC

OUTPUT

DRIVERS

SHIFT REGISTER AND CORRECTION

MSBINV

OGND

OVDD

0.5V TO

D11

CLKOUT

1743 F01

INPUT

S/H

FIRST STAGE

SENSE

VCM

AIN

–

AIN

4.7

µF

SECOND STAGE

THIRD STAGE

FOURTH STAGE

•

5-BIT

PIPELINED

ADC STAGE

4-BIT

PIPELINED

ADC STAGE

4-BIT

PIPELINED

ADC STAGE

2-BIT

FLASH

ADC

CONTROL

LOGIC

REFLA

REFHB

4.7

µF

µF1µF

0.1

µF

0.1

µF

REFHA

REFLB

REF

BUF

DIFF

REF

AMP

Figure 1. Functional Block Diagram

LTC1743CFW Datasheet(PDF) 12 Page - Linear Technology

LTC1743CFW Datasheet(HTML) 12 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL