LTC1744CFW datasheet(12/24 Pages) LINER

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LTC1744

1744f

APPLICATIO S I FOR ATIO

Figure 1. Block Diagram

DIFF

REF

AMP

REF

BUF

4.7

µF

0.1

µF

0.1

µF

INTERNAL CLOCK SIGNALS

REFL

REFH

DIFFERENTIAL

INPUT

LOW JITTER

CLOCK

DRIVER

RANGE

SELECT

2.5V

REFERENCE

5-BIT

PIPELINED

ADC STAGE

FIRST STAGE

4-BIT

PIPELINED

ADC STAGE

SECOND STAGE

4-BIT

PIPELINED

ADC STAGE

THIRD STAGE

4-BIT

FLASH

ADC

FOURTH STAGE

ENC

REFHA

REFLB

REFLA REFHB

ENC

SHIFT REGISTER

AND CORRECTION

MSBINV

OGND

OVDD 0.5V TO

D13

CLKOUT

1744 F01

INPUT

S/H

SENSE

VCM

AIN

–

AIN

4.7

µF

OUTPUT

DRIVERS

CONTROL LOGIC

AND

CALIBRATION LOGIC

•

The LTC1744 has two phases of operation, determined by

the state of the differential ENC/ENC input pins. For brev-

ity, the text will refer to ENC greater than ENC as ENC high

and ENC less than ENC as ENC low.

Each pipelined stage shown in Figure 1 contains an ADC,

a reconstruction DAC and an interstage residue amplifier.

In operation, the ADC quantizes the input to the stage and

the quantized value is subtracted from the input by the

DAC to produce a residue. The residue is amplified and

output by the residue amplifier. Successive stages operate

out of phase so that when the odd stages are outputting

their residue, the even stages are acquiring that residue

and visa versa.

When ENC is low, the analog input is sampled differentially

directly onto the input sample-and-hold capacitors, inside

the “Input S/H” shown in the block diagram. At the instant

that ENC transitions from low to high, the sampled input

is held. While ENC is high, the held input voltage is

buffered by the S/H amplifier which drives the first pipelined

ADC stage. The first stage acquires the output of the S/H

during this high phase of ENC. When ENC goes back low,

the first stage produces its residue which is acquired by

the second stage. At the same time, the input S/H goes

back to acquiring the analog input. When ENC goes back

high, the second stage produces its residue which is

acquired by the third stage. An identical process is re-

peated for the third stage, resulting in a third stage residue

that is sent to the fourth stage ADC for final evaluation.

Each ADC stage following the first has additional range to

accommodate flash and amplifier offset errors. Results

from all of the ADC stages are digitally delayed such that

the results can be properly combined in the correction

logic before being sent to the output buffer.

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample Hold Operation

Figure 2 shows an equivalent circuit for the LTC1744

CMOS differential sample-and-hold. The differential ana-

log inputs are sampled directly onto sampling capacitors

(CSAMPLE) through CMOS transmission gates. This direct

capacitor sampling results in lowest possible noise for a

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