LTC1748 datasheet(16/20 Pages) LINER

16 / 20 page

LTC1748

1748fa

At sample rates slower than 80Msps the duty cycle can

vary from 50% as long as each half cycle is at least 6ns.

The lower limit of the LTC1748 sample rate is determined

by droop of the sample-and-hold circuits. The pipelined

architecture of this ADC relies on storing analog signals on

small valued capacitors. Junction leakage will discharge

the capacitors. The specified minimum operating fre-

quency for the LTC1748 is 1Msps.

DIGITAL OUTPUTS

Digital Output Buffers

Figure 9 shows an equivalent circuit for a single output

buffer. Each buffer is powered by OVDD and OGND, iso-

lated from the ADC power and ground. The additional

N-channel transistor in the output driver allows operation

down to low voltages. The internal resistor in series with

the output makes the output appear as 50

Ω to external

circuitry and may eliminate the need for external damping

resistors.

Output Loading

As with all high speed/high resolution converters the

digital output loading can affect the performance. The

digital outputs of the LTC1748 should drive a minimal

capacitive load to avoid possible interaction between the

digital outputs and sensitive input circuitry. The output

should be buffered with a device such as an ALVCH16373

CMOS latch. For full speed operation the capacitive load

should be kept under 10pF. A resistor in series with the

APPLICATIO S I FOR ATIO

output may be used but is not required since the ADC has

a series resistor of 43

Ω on chip.

Lower OVDD voltages will also help reduce interference

from the digital outputs.

Format

The LTC1748 parallel digital output can be selected for

offset binary or 2’s complement format. The format is

selected with the MSBINV pin; high selects offset binary.

Overflow Bit

An overflow output bit indicates when the converter is

overranged or underranged. When OF outputs a logic high

the converter is either overranged or underranged.

Output Clock

The ADC has a delayed version of the ENC input available

as a digital output, CLKOUT. The CLKOUT pin can be used

to synchronize the converter data to the digital system.

This is necessary when using a sinusoidal encode. Data

will be updated just after CLKOUT falls and can be latched

on the rising edge of CLKOUT.

Output Driver Power

Separate output power and ground pins allow the output

drivers to be isolated from the analog circuitry. The power

supply for the digital output buffers, OVDD, should be tied

to the same power supply as for the logic being driven. For

example if the converter is driving a DSP powered by a 3V

supply then OVDD should be tied to that same 3V supply.

LTC1748

1748 F09

OVDD

VDD

0.1

µF

Ω

TYPICAL

DATA

OUTPUT

OGND

OVDD

0.5V TO

VDD

PREDRIVER

LOGIC

DATA

FROM

LATCH

Figure 9. Equivalent Circuit for a Digital Output Buffer

LTC1748 Datasheet(PDF) 16 Page - Linear Technology

LTC1748 Datasheet(HTML) 16 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL