M41ST95YMX6F datasheet(10/35 Pages) STMICROELECTRONICS

10 / 35 page

M41ST95Y*, M41ST95W

10/35

Signal Description

Serial Data Output (SDO). The

output

used to transfer data serially out of the Memory.

Data is shifted out on the falling edge of the serial

clock.

Serial Data Input (SDI). The input pin is used to

transfer data serially into the device. Instructions,

addresses, and the data to be written, are each re-

ceived this way. Input is latched on the rising edge

of the serial clock.

Serial Clock (SCL). The serial clock provides the

timing for the serial interface (as shown in Figure

9., page 11 and Figure 10., page 11). The W/R

Bit, addresses, or data are latched, from the input

pin, on the rising edge of the clock input. The out-

put data on the SDO pin changes state after the

falling edge of the clock input.

The M41ST95Y/W can be driven by a microcon-

troller with its SPI peripheral running in either of

the two following modes:

(CPOL, CPHA) = ('0', '0') or

(CPOL, CPHA) = ('1', '1').

For these two modes, input data (SDI) is latched in

by the low-to-high transition of clock SCL, and out-

put data (SDO) is shifted out on the high-to-low

transition of SCL (see Table 2 and Figure 8).

Chip Enable (E). When E is high, the memory

device is deselected, and the SDO output pin is

held in its high impedance state.

After power-on, a high-to-low transition on E is re-

quired prior to the start of any operation.

Table 2. Function Table

Note: 1. SDO remains at High Z until eight bits of data are ready to be shifted out during a READ.

Figure 8. Data and Clock Timing

Mode

SCL

SDI

SDO

Disable Reset

Input Disabled

High Z

WRITE

Data Bit latch

High Z

READ

Next data bit shift (1)

AI04630

AI04631

AI06368

SCL

MSB

LSB

CPHA

SDI

CPOL

MSB

LSB

SDO

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