32-Channel Sample/Hold Amplifier

with Four Multiplexed Inputs

6

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_______________Detailed Description

The MAX5166 connects four separate analog inputs to

four internal 1-to-8 analog multiplexers. Each multiplex-

er channel connects to a buffered sample/hold circuit

and a series output resistor, creating a four-input

device with 32 sample/hold output channels. Three

multiplexer channel-address inputs and four mode-

select inputs (one for each multiplexer) control channel

selection and sample/hold functions (Figure 1 and

Tables 1 and 2).

Digital Interface

Three address pins and 3-to-8 address decoder logic

select the channel for all four internal analog multiplex-

ers. The mode-select inputs (M3–M0) independently

control the sample/hold functions for each multiplexer

(Tables 1 and 2).

Sample/Hold

The MAX5166 contains 32 buffered sample/hold cir-

cuits with internal hold capacitors. Internal hold capaci-

tors minimize leakage current, dielectric absorption,

feedthrough, and required board space. The value of

the hold capacitor affects acquisition time, hold step,

and droop rate. Lower capacitance allows faster acqui-

sition times but increases the droop rate. Higher values

increase hold time and acquisition time. The hold

capacitor used in the MAX5166 provides fast 2.5µs

(typ) acquisition time while maintaining a low 1mV/sec

(typ) droop rate, making the sample/hold ideal for high-

speed sampling.

Sample Mode

Driving M3–M0 low (one at a time) selects sample

mode (Tables 1 and 2). During sample mode, the

selected multiplexer channel connects to IN_ allowing

the hold capacitor to acquire the input signal. To guar-

antee an accurate sample, maintain sample mode for

at least 4µs. Sampling for longer than 4µs results in

tracking. Only the addressed channel on the selected

multiplexer samples the input; all other channels remain

in hold mode.

Hold Mode

Driving M3–M0 high selects hold mode. Hold mode dis-

ables the multiplexer, which disconnects all eight chan-

nels on the 1-to-8 multiplexer from the input. When a

channel is disconnected, the hold capacitor maintains

the sampled voltage at the output with a 1mV/sec

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NAME

FUNCTION

1, 47, 48

A2, A0, A1

Address Inputs. The input of a 3-to-8 decoder that controls channel selection for all four 1-to-8

multiplexers. Selects which output channels are connected to the input during sample mode

(Tables 1, 2).

PIN

Pin Description

2–5

M0–M3

Mode-Selection/Multiplexer-Enable Inputs 0 to 3. All four 1-to-8 multiplexers are independently

controlled. A logic low enables sample mode by connecting the selected channel to IN_. A logic

high enables hold mode (Tables 1, 2).

6

Positive Digital Logic Power-Supply Input

7

DGND

Digital Ground

8

Negative Analog Power-Supply Input

9

AGND

Analog Ground

10–13

IN3–IN0

Analog Inputs 0 to 3

14–29

OUT0–OUT15

Outputs 0 to 15

30

Positive Analog Power-Supply Input

31–46

OUT16–OUT31

Outputs 16 to 31